PIC18LF26J53-I/SP Microchip Technology, PIC18LF26J53-I/SP Datasheet - Page 196

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PIC18LF26J53-I/SP

Manufacturer Part Number
PIC18LF26J53-I/SP
Description
28-pin, USB, 64KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC 28 SPDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18LF26J53-I/SP

Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.75 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18F47J53 FAMILY
11.3.11
This section contains a number of timing examples that
represent the common Master mode configuration
options. These options vary from 8-bit to 16-bit data,
fully demultiplexed to fully multiplexed address and
Wait states.
FIGURE 11-12:
FIGURE 11-13:
FIGURE 11-14:
DS39964B-page 196
PMD<7:0>
PMA<7:0>
PMD<7:0>
WAITB<1:0> = 01
PMCS1
PMWR
PMPIF
PMD<7:0>
PMRD
BUSY
PMCS1
PMALL
PMWR
PMPIF
PMRD
BUSY
MASTER MODE TIMING
PMCS1
PMALL
PMWR
PMPIF
PMRD
BUSY
Q1
Q1
Q2 Q3 Q4
Q1- - -
READ AND WRITE TIMING, 8-BIT DATA, DEMULTIPLEXED ADDRESS
READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS
READ TIMING, 8-BIT DATA, WAIT STATES ENABLED,
PARTIALLY MULTIPLEXED ADDRESS
Q2 Q3 Q4
Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - -
Q1
Q2 Q3 Q4
Q1
Address<7:0>
Address<7:0>
Q2 Q3 Q4
Q1
Q2 Q3 Q4
Q1
Preliminary
Q2 Q3 Q4
WAITM<3:0> = 0010
Q1
Data
Q2 Q3 Q4
WAITE<1:0> = 00
Q1
Q2 Q3 Q4
Q1
Data
Q2 Q3 Q4
Q1
Q2 Q3 Q4
Q1
 2010 Microchip Technology Inc.
Q2 Q3 Q4
Q1
Q1
Q2 Q3 Q4
Q2 Q3 Q4

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