PIC18LF13K50T-I/SS Microchip Technology, PIC18LF13K50T-I/SS Datasheet - Page 80
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PIC18LF13K50T-I/SS
Manufacturer Part Number
PIC18LF13K50T-I/SS
Description
8 KB Flash, 512 RAM, 15 I/O, 10-bit ADC, USB 2.0, NanoWatt XLP 20 SSOP .209in T/
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(40 pages)
3.PIC18F13K50-ISS.pdf
(10 pages)
4.PIC18F13K50-ISS.pdf
(2 pages)
Specifications of PIC18LF13K50T-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F/LF1XK50
7.9
External interrupts on the RC0/INT0, RC1/INT1 and
RC2/INT2
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge; if
the bit is clear, the trigger is on the falling edge. When
a valid edge appears on the RCx/INTx pin, the
corresponding flag bit, INTxF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxE. Flag bit, INTxF, must be cleared by software in
the Interrupt Service Routine before re-enabling the
interrupt.
All external interrupts (INT0, INT1 and INT2) can wake-
up the processor from Idle or Sleep modes if bit INTxE
was set prior to going into those modes. If the Global
Interrupt Enable bit, GIE, is set, the processor will
branch to the interrupt vector following wake-up.
Interrupt priority for INT1 and INT2 is determined by
the value contained in the interrupt priority bits,
INT1IP and INT2IP of the INTCON3 register. There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
EXAMPLE 7-1:
DS41350E-page 80
MOVWF
MOVFF
MOVFF
;
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
INTn Pin Interrupts
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
pins
are
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
edge-triggered.
If
Preliminary
the
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
7.10
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L regis-
ter pair (FFFFh 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE of the INTCON register. Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP of the INTCON2 register.
See
on the Timer0 module.
7.11
An input change on PORTA or PORTB sets flag bit,
RABIF of the INTCON register. The interrupt can be
enabled/disabled by setting/clearing enable bit, RABIE
of the INTCON register. Pins must also be individually
enabled with the IOCA and IOCB register. Interrupt
priority for PORTA and PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RABIP of the INTCON2 register.
7.12
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see
“Data Memory
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved.
STATUS and BSR registers during an Interrupt Service
Routine.
Section 10.0 “Timer0 Module”
Example 7-1
TMR0 Interrupt
PORTA and PORTB Interrupt-on-
Change
Context Saving During Interrupts
Organization”), the user may need to
saves and restores the WREG,
2010 Microchip Technology Inc.
for further details
Section 3.3
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