PIC18F96J65-I/PF Microchip Technology, PIC18F96J65-I/PF Datasheet - Page 10
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PIC18F96J65-I/PF
Manufacturer Part Number
PIC18F96J65-I/PF
Description
96KB Flash, 12KB RAM, 10BASE-T Ethernet 100 TQFP 14x14x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(8 pages)
3.PIC18F66J65-IPT.pdf
(480 pages)
4.PIC18F66J65-IPT.pdf
(4 pages)
5.PIC18F66J65-IPT.pdf
(10 pages)
6.PIC18F96J60-IPT.pdf
(24 pages)
Specifications of PIC18F96J65-I/PF
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
96KB (48K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F96J65-I/PF
Manufacturer:
Microchip
Quantity:
251
Company:
Part Number:
PIC18F96J65-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F97J60 FAMILY
3.1.2
It is possible to erase a single row (1024 bytes of data),
provided the block is not code-protected. Rows are
located at static boundaries beginning at program
memory address 000000h, extending to the internal
program memory limit (see Section 2.2 “Memory
Maps”).
The Row Erase duration is internally timed. After the
WR bit in EECON1 is set, a NOP is issued, where the
4th PGC is held high for the duration of the Row Erase
time, P10.
The code sequence to Row Erase a PIC18F97J60 fam-
ily device is shown in Table 3-2. The flowchart shown in
Figure 3-3 depicts the logic necessary to completely
erase a PIC18F97J60 family device. The timing diagram
that details the “Row Erase” operation and parameter
P10 is shown in Figure 3-4.
TABLE 3-2:
FIGURE 3-4:
DS39688D-page 10
Step 1: Enable memory writes.
Step 2: Point to first row in code memory.
Step 3: Enable erase and erase single row.
Step 4: Repeat step 3, with Address Pointer incremented by 1024 until all rows are erased.
Note:
Command
PGC
PGD
0000
0000
0000
0000
0000
0000
0000
4-Bit
ICSP ROW ERASE
The TBLPTR register can point at any byte
within the row intended for erase.
1
4-Bit Command
0
2
0
84 A6
6A F8
6A F7
6A F6
88 A6
82 A6
00 00
ERASE CODE MEMORY CODE SEQUENCE
3
0
Data Payload
SET WR AND START ROW-ERASE TIMING
4
0
P5
1
0
2
1
3
16-Bit Data Payload
BSF
CLRF
CLRF
CLRF
BSF
BSF
NOP – hold PGC high for time P10.
1
4
0
5
EECON1, WREN
TBLPTRU
TBLPTRH
TBLPTRL
EECON1, FREE
EECON1, WR
0
6
1
PGD = Input
15
0
16
1
P5A
FIGURE 3-3:
Addr = Addr + 1024
4-Bit Command
1
0
2
Core Instruction
0
3
0
0
Row-Erase Time
ROW ERASE CODE
MEMORY FLOW
P10
© 2009 Microchip Technology Inc.
No
Start Erase Sequence
and Hold PGC High
4
for Time P10
Row Erase
Device for
Configure
P5
Done?
Rows
Done
Start
All
Data Payload
1
Yes
Addr = 0
0
16-Bit
2
0
3
0