PIC18F45K80-E/P Microchip Technology, PIC18F45K80-E/P Datasheet - Page 483
![ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 40 PDIP .600in TUBE](/photos/16/3/160374/pdip40_sml.jpg)
PIC18F45K80-E/P
Manufacturer Part Number
PIC18F45K80-E/P
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 40 PDIP .600in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F45K80-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC18F45K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F45K80-E/PT
Manufacturer:
NichTek
Quantity:
120 000
Company:
Part Number:
PIC18F45K80-E/PT
Manufacturer:
MICROCH
Quantity:
200
Company:
Part Number:
PIC18F45K80-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 483 of 628
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28.6
The user program memory is divided into four blocks.
One of these is a boot block of 1 or 2 Kbytes. The
remainder of the memory is divided into blocks on
binary boundaries.
FIGURE 28-6:
2011 Microchip Technology Inc.
Note 1: Sizes of memory areas are not to scale.
000000h
01FFFFh
200000h
3FFFFFh
Program Verification and
Code Protection
2: Boot block size is determined by the BBSIZ0 bit (CONFIG4L<4>).
Unimplemented
Code Memory
Configuration
Read as ‘
and ID
Space
CODE-PROTECTED PROGRAM MEMORY FOR THE PIC18F66K80 FAMILY
0
’
Preliminary
Boot Block
BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0
Block 0
Block 1
Block 2
Block 3
2 kW
6 kW
8 kW
8 kW
8 kW
PIC18F66K80 FAMILY
PIC18FX6K80
Each of the blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPx)
• Write-Protect bit (WRTx)
• External Block Table Read bit (EBTRx)
Figure 28-6
48, 64, 96 and 128 Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in
Device/Memory Size
Boot Block Boot Block
Block 0
Block 1
Block 2
Block 3
7 kW
8 kW
8 kW
8 kW
shows the program memory organization for
Block 0
Block 1
Block 2
Block 3
2 kW
2 kW
4 kW
4 kW
4 kW
PIC18FX5K80
(1)
Boot Block 0000h
Block 0
Block 1
Block 2
Block 3
3 kW
4 kW
4 kW
4 kW
DS39977C-page 483
0800h
1000h
1FFFh
2000h
3FFFh
4000h
5FFFh
6000h
7FFFh
8000h
BFFFh
C000h
FFFFh
10000h
13FFFh
14000h
17FFFh
18000h
1BFFFh
1C000h
1FFFFh
Table
Address
28-4.
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