PIC18F45K80-E/P Microchip Technology, PIC18F45K80-E/P Datasheet - Page 336
PIC18F45K80-E/P
Manufacturer Part Number
PIC18F45K80-E/P
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 40 PDIP .600in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F45K80-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC18F45K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F45K80-E/PT
Manufacturer:
NichTek
Quantity:
120 000
Company:
Part Number:
PIC18F45K80-E/PT
Manufacturer:
MICROCH
Quantity:
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Part Number:
PIC18F45K80-E/PT
Manufacturer:
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Quantity:
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PIC18F66K80 FAMILY
21.4.17.3
Bus collision occurs during a Stop condition if:
a)
b)
FIGURE 21-33:
FIGURE 21-34:
DS39977C-page 336
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
SDA
SCL
PEN
BCLIF
P
SSPIF
SDA
SCL
PEN
BCLIF
P
SSPIF
Bus Collision During a Stop
Condition
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA asserted low
Assert SDA
T
BRG
T
BRG
Preliminary
T
BRG
T
BRG
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘ 0 ’
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘ 0 ’
SCL goes low before SDA goes high,
set BCLIF
T
BRG
T
BRG
(Figure
2011 Microchip Technology Inc.
21-33). If the SCL pin is
(Figure
SDA sampled
low after T
set BCLIF
‘0’
‘0’
‘0’
‘0’
21-34).
BRG
,
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