PIC18F45K20-E/P Microchip Technology, PIC18F45K20-E/P Datasheet - Page 9

• Manufacturer Part Number: PIC18F45K20-E/P
• Description: 32KB, Flash, 1536bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 PDIP .600in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K20-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240313 - BOARD DEMO 8BIT XLPAC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

31. Module: MSSP SPI
32. Module: MSSP SPI
33. Module: MSSP SPI
 2010 Microchip Technology Inc.
signal improperly starts immediately with the direc-
tion change and stays on for T
Prescale * DC1B[1:0].
Work around
Avoid changing direction when the duty cycle is
within three Least Significant steps of 100% duty
cycle. Instead, clear the DC1B[1:0] bits before the
direction change and then set them to the desired
value after the direction change is complete.
Affected Silicon Revisions
When the SPI clock is configured for Timer2/2
(SSPCON1<3:0> = 0011) and the CKE bit of the
SSPSTAT register is ‘1’, then when SSPBUF is
written, the SCK output is improperly immediately
driven to the non-Idle state together with the MSb
value of the SSPBUF. The duration at which SDO
and SCK remain at these levels may be shorter
than a full half-bit period. The remaining bits in the
byte are output properly.
Work around
None.
Affected Silicon Revisions
In SPI Master mode, when the CKE bit of the SSP-
STAT register is cleared and the SMP bit of the
SSPSTAT register is set, then the last bit of the
incoming data stream (bit 0) at the SDI pin will not
be sampled properly.
Work around
None.
Affected Silicon Revisions
In SPI Master mode, if the SSPBUF register is
written while a byte is actively being transmitted,
an extra clock pulse will be improperly generated
at the end of the transmission. Further writes to the
PIC18F24K20/25K20/44K20/45K20
X
X
X
X
X
X
OSC
X
X
X
* TMR2
X
X
X
SSPBUF register will be inhibited although 8 or 9
clock pulses will be generated for each attempted
write. The WCON bit of the SSPCON register is
properly set indicating that a write collision
occurred. However, the write collision condition
can only be cleared by resetting the MSSP
module. Clear the MSSP by clearing the SSPEN
bit of the SSPCON1 register.
Work around
Use the SSPIF bit of the PIR1 register or the BF bit
of the SSPSTAT register to determine that the
transmission is complete before writing the
SSPBUF register. In the event that a write collision
does occur, use the slave select feature to
resynchronize the slave clock.
Affected Silicon Revisions
X
DS80425G-page 9
X
X
X