PIC18F45K20-E/P Microchip Technology, PIC18F45K20-E/P Datasheet - Page 5

• Manufacturer Part Number: PIC18F45K20-E/P
• Description: 32KB, Flash, 1536bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 PDIP .600in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K20-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240313 - BOARD DEMO 8BIT XLPAC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7. Module: MSSP I
8. Module: MSSP SPI
9. Module: MSSP SPI
10. Module: MSSP SPI
 2010 Microchip Technology Inc.
I
Work around
Use software to emulate Master mode.
Affected Silicon Revisions
In SPI Master mode, when the CKE bit is cleared
and the SMP bit is set, the last bit of the incoming
data stream (bit 0) at the SDI pin will not be
sampled properly.
Work around
None.
Affected Silicon Revisions
In SPI Master mode, when CKE bit is set, the
SSPBUF will reload the SSPSR output shift
register on every high-to-low transition of the SS
pin.
Work around
Avoid using the SS pin when the CKE bit is set and
the MSSP is configured for SPI Master mode.
Affected Silicon Revisions
When SPI is enabled in Master mode with
CKE = 1 and CKP = 0, a 1/F
occur on the SCK pin.
Work around
Configure SCK pin as an input until after the MSSP
is setup.
Affected Silicon Revisions
2
C Master mode is not functional (Rev. A4 only).
X
X
X
X
X
X
X
X
X
X
X
X
2
X
X
X
X
C
PIC18F24K20/25K20/44K20/45K20
OSC
wide pulse will
11. Module: EUSART
12. Module: EUSART
13. Module: EUSART
In Synchronous Master mode, when the SPBRG is
set to an odd number, the duty cycle of the CK
output will be skewed by one baud clock count.
Work around
High values of SPBRG will minimize the effect of
this anomaly.
Affected Silicon Revisions
In Synchronous Master mode, when the SPBRG is
set to 3 and the TXREG is written while the
previous character is still in the TX shift register,
the LS bit of the TXREG character may be
corrupted during transmission.
Work around
When SPBRG is set to 3, wait until the TRMT bit of
the TXSTA register is set before loading TXREG
with the next character to be transmitted.
Affected Silicon Revisions
In Synchronous Master mode, if the SPBRG
register is equal to 0 when the TXEN bit is set, then
writing to TXREG will properly start transmission.
However, the clock will be improperly out of phase
with the data bits and the clock will not stop at the
end of the character transmission.
Work around
Set SPBRG register to non-zero value before
setting the TXEN bit.
Affected Silicon Revisions
X
X
X
X
X
X
X
X
X
X
X
X
DS80425G-page 5