PIC18F13K50T-I/SO Microchip Technology, PIC18F13K50T-I/SO Datasheet - Page 76

• Manufacturer Part Number: PIC18F13K50T-I/SO
• Description: 8 KB Flash, 512 RAM, 15 I/O, 10-bit ADC, USB 2.0 20 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K50T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOIC
• Lead Free Status / Rohs Status: Details

PIC18F/LF1XK50
REGISTER 7-7:
DS41350E-page 76
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OSCFIE
R/W-0
OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
C1IE: Comparator C1 Interrupt Enable bit
1 = Enabled
0 = Disabled
C2IE: Comparator C2 Interrupt Enable bit
1 = Enabled
0 = Disabled
EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1 = Enabled
0 = Disabled
BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
USBIE: USB Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
Unimplemented: Read as ‘0’
R/W-0
C1IE
PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2
W = Writable bit
‘1’ = Bit is set
R/W-0
C2IE
R/W-0
EEIE
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
BCLIE
R/W-0
USBIE
R/W-0
 2010 Microchip Technology Inc.
x = Bit is unknown
TMR3IE
R/W-0
U-0
—
bit 0