PIC18F13K50T-I/SO Microchip Technology, PIC18F13K50T-I/SO Datasheet - Page 180

• Manufacturer Part Number: PIC18F13K50T-I/SO
• Description: 8 KB Flash, 512 RAM, 15 I/O, 10-bit ADC, USB 2.0 20 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K50T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOIC
• Lead Free Status / Rohs Status: Details

PIC18F/LF1XK50
TABLE 15-4:
DS41350E-page 180
IPR1
PIR1
PIE1
IPR2
PIR2
PIE2
SSPADD
SSPBUF
SSPCON1
SSPCON2
SSPMSK
SSPSTAT
TRISB
Legend:
Name
— = unimplemented, read as ‘0’. Shaded cells are not used by I
SSP Address Register in I
Mode.
SSP Receive Buffer/Transmit Register
OSCFIP
OSCFIE
OSCFIF
TRISB7
WCOL
GCEN
MSK7
Bit 7
SMP
—
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH I
ACKSTAT
SSPOV
TRISB6
MSK6
ADIP
ADIE
Bit 6
ADIF
C1IP
C1IF
C1IE
CKE
2
SSPEN
ACKDT
TRISB5
MSK5
C™ Slave Mode. SSP Baud Rate Reload Register in I
RCIP
RCIF
RCIE
Bit 5
C2IP
C2IF
C2IE
D/A
TRISB4
ACKEN
Preliminary
MSK4
EEIP
EEIE
Bit 4
TXIP
TXIF
TXIE
EEIF
CKP
P
SSPM3
SSPIP
SSPIE
SSPIF
BCLIP
BCLIF
BCLIE
RCEN
MSK3
Bit 3
—
S
2
CCP1IP
CCP1IE
CCP1IF
SSPM2
C™.
USBIP
USBIF
USBIE
MSK2
Bit 2
PEN
R/W
2
—
C™
TMR2IP
TMR2IF
TMR2IE
TMR3IP
TMR3IF
TMR3IE
SSPM1
RSEN
 2010 Microchip Technology Inc.
MSK1
Bit 1
UA
—
2
C Master
TMR1IP
TMR1IF
TMR1IE
SSPM0
MSK0
Bit 0
SEN
BF
—
—
—
—
Values
Reset
page
288
288
288
288
288
288
286
286
286
286
288
286
288
on