PIC16LF1507-I/SO Microchip Technology, PIC16LF1507-I/SO Datasheet - Page 195
![3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 SOIC .300in TUBE](/photos/16/12/161297/soic20_sml.jpg)
PIC16LF1507-I/SO
Manufacturer Part Number
PIC16LF1507-I/SO
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F1507-EML.pdf
(266 pages)
Specifications of PIC16LF1507-I/SO
Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOIC-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
- Current page: 195 of 266
- Download datasheet (3Mb)
PIC16(L)F1507
22.11 Configuring the CWG
The following steps illustrate how to properly configure
the CWG to ensure a synchronous start:
1.
2.
3.
4.
5.
6.
7.
8.
9.
DS41586A-page 195
Ensure that the TRIS control bits corresponding
to CWGxA and CWGxB are set so that both are
configured as inputs.
Clear the GxEN bit, if not already cleared.
Set desired dead-band times with the CWGxDBR
and CWGxDBF registers.
Setup the following controls in CWGxCON2
auto-shutdown register:
Select the desired input source using the
CWGxCON1 register.
Configure the following controls in CWGxCON0
register:
Set the GxEN bit.
Clear TRIS control bits corresponding to
CWGxA and CWGxB to be used to configure
those pins as outputs.
If auto-restart is to be used, set the GxARSEN
bit and the GxASE bit will be cleared automati-
cally. Otherwise, clear the GxASE bit to start the
CWG.
• Select desired shutdown source.
• Select both output overrides to the desired
• Set the GxASE bit and clear the GxARSEN
• Select desired clock source.
• Select the desired output polarities.
• Set the output enables for the outputs to be
levels (this is necessary even if not using
auto-shutdown because start-up will be from
a shutdown state).
bit.
used.
Preliminary
22.11.1
The levels driven to the output pins, while the shutdown
input is true, are controlled by the GxASDLA and
GxASDLB
(Register
override level and GxASDLB controls the CWG1B
override level. The control bit logic level corresponds to
the output logic drive level while in the shutdown state.
The polarity control does not apply to the override level.
22.11.2
After an auto-shutdown event has occurred, there are
two ways to have resume operation:
• Software controlled
• Auto-restart
The restart method is selected with the GxARSEN bit
of the CWGxCON2 register. Waveforms of software
controlled and automatic restarts are shown in
Figure 22-5
22.11.2.1
When the GxARSEN bit of the CWGxCON2 register is
cleared, the CWG must be restarted after an auto-shut-
down event by software.
Clearing the shutdown state requires all selected shut-
down inputs to be low, otherwise the GxASE bit will
remain set. The overrides will remain in effect until the
first rising edge event after the GxASE bit is cleared.
The CWG will then resume operation.
22.11.2.2
When the GxARSEN bit of the CWGxCON2 register is
set, the CWG will restart from the auto-shutdown state
automatically.
The GxASE bit will clear automatically when all shut-
down sources go low. The overrides will remain in
effect until the first rising edge event after the GxASE
bit is cleared. The CWG will then resume operation.
22-3). GxASDLA controls the CWG1A
PIN OVERRIDE LEVELS
AUTO-SHUTDOWN RESTART
and
bits
Software controlled restart
Auto-Restart
Figure
of
22-6.
2011 Microchip Technology Inc.
the
CWGxCON2
register
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