PIC16LF1507-I/SO Microchip Technology, PIC16LF1507-I/SO Datasheet - Page 152
![3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 SOIC .300in TUBE](/photos/16/12/161297/soic20_sml.jpg)
PIC16LF1507-I/SO
Manufacturer Part Number
PIC16LF1507-I/SO
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F1507-EML.pdf
(266 pages)
Specifications of PIC16LF1507-I/SO
Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOIC-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
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18.1
The clock input to the Timer2 module is the system
instruction clock (F
TMR2 increments from 00h on each clock edge.
A 4-bit counter/prescaler on the clock input allows direct
input, divide-by-4 and divide-by-16 prescale options.
These options are selected by the prescaler control bits,
T2CKPS<1:0> of the T2CON register. The value of
TMR2 is compared to that of the Period register, PR2, on
each clock cycle. When the two values match, the
comparator generates a match signal as the timer
output. This signal also resets the value of TMR2 to 00h
on
counter/postscaler
Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESET Instruction
18.2
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match)
provides the input for the 4-bit counter/postscaler. This
counter generates the TMR2 match interrupt flag which
is latched in TMR2IF of the PIR1 register. The interrupt
is enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE of the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0>, of the T2CON register.
2011 Microchip Technology Inc.
Note:
the
Timer2 Operation
Timer2 Interrupt
next
TMR2 is not cleared when T2CON is
written.
cycle
OSC
(see
/4).
and
Section 18.2
drives
the
“Timer2
output
Preliminary
18.3
The unscaled output of TMR2 is available primarily to
the PWMx module, where it is used as a time base for
operation.
18.4
Timer2 cannot be operated while the processor is in
Sleep mode. The contents of the TMR2 and PR2
registers will remain unchanged while the processor is
in Sleep mode.
Timer2 Output
Timer2 Operation During Sleep
PIC16(L)F1507
DS41586A-page 152
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