PIC16F721T-I/SS Microchip Technology, PIC16F721T-I/SS Datasheet - Page 18

• Manufacturer Part Number: PIC16F721T-I/SS
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721T-I/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF720/721
TABLE 2-1:
DS41430A-page 18
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note 1:
Address
Bank 1
(
(
(
(
(5)
(
(
(
2
2
2
2
3
1
2
)
)
)
)
)
),(
)
2:
3:
4:
5:
2
)
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
These registers can be addressed from any bank.
Accessible only when SSPM<3:0> = 1001.
This bit is unimplemented and reads as ‘1’.
See
INDF
OPTION_
REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
T1GCON
OSCCON
OSCTUNE
PR2
SSPADD
SSPMSK
SSPSTAT
WPUA
IOCA
TXSTA
SPBRG
FVRCON
ADCON1
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Register
Name
—
—
—
—
—
—
—
—
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
6-2.
TMR1GIE
TMR1GE
FVRRDY
TRISC7
RABPU
TRISB7
CSRC
BRG7
Bit 7
SMP
IRP
GIE
—
—
—
—
—
—
—
—
Addressing this location uses contents of FSR to address data memory (not a physical register)
T1GPOL
INTEDG
TRISB6
TRISC6
FVREN
ADCS2
BRG6
Bit 6
PEIE
ADIE
CKE
RP1
TX9
—
—
—
—
—
—
—
TMR0IE
TRISA5
TRISB5
TRISC5
WPUA5
Program Counter (PC) Least Significant Byte
T1GTM
ADCS1
IRCF1
IOCA5
BRG5
T0CS
TUN5
TXEN
TSEN
RCIE
Bit 5
RP0
D/A
—
—
Indirect Data Memory Address Pointer
Timer2 module Period Register
T1GSPM
TRISC4
WPUA4
TRISA4
TRISB4
TSRNG
ADCS0
Unimplemented
Unimplemented
Unimplemented
IRCF0
IOCA4
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
SYNC
BRG4
TUN4
T0SE
Bit 4
Write Buffer for the upper 5 bits of the Program Counter
INTE
TXIE
TO
—
ADD<7:0>
MSK<7:0>
P
T1GGO/
TRISC3
WPUA3
Note 4
RABIE
SSPIE
DONE
IOCA3
BRG3
TUN3
Bit 3
ICSL
PSA
PD
—
—
—
—
—
S
T1GVAL
TRISC2
TMR0IF
CCP1IE
WPUA2
TRISA2
IOCA2
BRGH
BRG2
TUN2
Bit 2
ICSS
PS2
R/W
—
—
—
—
Z
ADFVR1
T1GSS1
TMR2IE
TRISA1
TRISC1
WPUA1
 2010 Microchip Technology Inc.
IOCA1
TRMT
BRG1
TUN1
INTF
Bit 1
POR
PS1
DC
UA
—
—
—
ADFVR0
T1GSS0
TMR1IE
TRISA0
TRISC0
WPUA0
RABIF
IOCA0
TUN0
BRG0
TX9D
Bit 0
BOR
PS0
BF
—
—
—
C
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
--11 -111
1111 ----
1111 1111
---0 0000
0000 000x
0000 0000
---- --qq
0000 0x00
--10 qq--
--00 0000
1111 1111
0000 0000
1111 1111
0000 0000
--11 1111
--00 0000
0000 -010
0000 0000
q000 --00
-000 ----
POR, BOR
Value on
—
—
—
—
—
—
—
—
Value on all
xxxx xxxx
1111 1111
0000 0000
000q quuu
uuuu uuuu
--11 -111
1111 ----
1111 1111
---0 0000
0000 000x
0000 0000
---- --uu
uuuu uxuu
--10 qq--
--uu uuuu
1111 1111
0000 0000
1111 1111
0000 0000
--11 1111
--00 0000
0000 -010
0000 0000
q000 --00
-000 ----
Resets
other
—
—
—
—
—
—
—
—