PIC16F707-I/MV Microchip Technology, PIC16F707-I/MV Datasheet - Page 80

• Manufacturer Part Number: PIC16F707-I/MV
• Description: 14KB Flash Program, MTouch, 32ch CSM, 1.8V-5.5V, 16MHz Internal Oscillator, 8b A
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ mTouch™ 16Fr

Specifications of PIC16F707-I/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 363 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC16F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16F707/PIC16LF707
9.1
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• Channel selection
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• Results formatting
9.1.1
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to Section 6.0
“I/O Ports” for more information.
9.1.2
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 9.2
“ADC Operation” for more information.
TABLE 9-1:
DS41418A-page 80
Legend: Shaded cells are outside of recommended range.
Note 1:
Clock Source
Note:
Fosc/16
Fosc/32
Fosc/64
ADC Clock Period (T
Fosc/2
Fosc/4
Fosc/8
ADC
F
2:
3:
4:
RC
ADC Configuration
The F
These values violate the minimum required T
For faster conversion times, the selection of another clock source is recommended.
When the device frequency is greater than 1 MHz, the F
conversion will be performed during Sleep.
PORT CONFIGURATION
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
CHANNEL SELECTION
RC
ADC CLOCK PERIOD (T
source has a typical T
ADCS<2:0>
000
100
001
101
010
110
x11
AD
)
1.0-6.0 s
100 ns
200 ns
400 ns
20 MHz
800 ns
1.6 s
3.2 s
AD
time of 1.6 s for V
AD
(2)
(2)
(2)
(1,4)
) V
Preliminary
S
1.0-6.0 s
. DEVICE OPERATING FREQUENCIES
125 ns
250 ns
0.5 s
AD
16 MHz
1.0 s
2.0 s
4.0 s
time.
(2)
(2)
(2)
9.1.3
The ADREF bits of the ADCON1 register provides
control of the positive voltage reference. The positive
voltage reference can be either V
voltage source or the internal Fixed Voltage Reference.
The negative voltage reference is always connected to
the ground reference. See Section 10.0 “Fixed
Voltage Reference” for more details on the Fixed
Voltage Reference.
9.1.4
The source of the conversion clock is software select-
able via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
• F
• F
• F
• F
• F
• F
• F
The time to complete one bit conversion is defined as
T
as shown in Figure 9-2.
For
specification must be met. Refer to the A/D conversion
requirements
Specifications” for more information. Table 9-1 gives
examples of appropriate ADC clock selections.
Device Frequency (F
(1,4)
AD
DD
Note:
OSC
OSC
OSC
OSC
OSC
OSC
RC
. One full 8-bit conversion requires 10 T
.
RC
correct
1.0-6.0 s
(dedicated internal oscillator)
/2
/4
/8
/16
/32
/64
clock source is only recommended if the
250 ns
500 ns
8.0 s
8 MHz
1.0 s
2.0 s
4.0 s
ADC VOLTAGE REFERENCE
Unless using the F
system clock frequency will change the
ADC
adversely affect the ADC result.
CONVERSION CLOCK
(3)
(2)
(2)
conversion,
(1,4)
in
clock
OSC
1.0-6.0 s
 2010 Microchip Technology Inc.
Section 25.0
16.0 s
500 ns
8.0 s
)
4 MHz
1.0 s
2.0 s
4.0 s
frequency,
the
RC
(3)
(2)
(3)
(1,4)
, any changes in the
appropriate
DD
1.0-6.0 s
, an external
which
16.0 s
32.0 s
64.0 s
8.0 s
1 MHz
2.0 s
4.0 s
“Electrical
AD
periods
(3)
(3)
(3)
(3)
may
(1,4)
T
AD