PIC16F707-I/MV Microchip Technology, PIC16F707-I/MV Datasheet - Page 163

• Manufacturer Part Number: PIC16F707-I/MV
• Description: 14KB Flash Program, MTouch, 32ch CSM, 1.8V-5.5V, 16MHz Internal Oscillator, 8b A
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ mTouch™ 16Fr

Specifications of PIC16F707-I/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 363 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC16F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.1.2.4
The SS pin allows Synchronous Slave mode operation.
The SPI must be in Slave mode with SS pin control
enabled (SSPM<3:0> = 0100). The associated TRIS bit
for the SS pin must be set, making SS an input.
In Slave Select mode, when:
• SS = 0, The device operates as specified in
• SS = 1, The SPI module is held in Reset and the
FIGURE 19-6:
 2010 Microchip Technology Inc.
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Section 19.1.2 “Slave Mode”.
SDO pin will be tri-stated.
Note 1: When the SPI is in Slave mode with SS pin
2: If the SPI is used in Slave mode with CKE
control enabled (SSPM<3:0> = 0100), the
SPI module will reset if the SS pin is driven
high.
set, the SS pin control must be enabled.
Slave Select Operation
SLAVE SELECT SYNCHRONIZATION WAVEFORM
bit 7
bit 7
bit 6
Preliminary
PIC16F707/PIC16LF707
When the SPI module resets, the bit counter is cleared
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit. Figure 19-6
shows the timing waveform for such a synchronization
event.
19.1.2.5
While in Sleep mode, the slave can transmit/receive
data. The SPI Transmit/Receive Shift register operates
asynchronously to the device on the externally supplied
clock source. This allows the device to be placed in
Sleep mode and data to be shifted into the SPI Trans-
mit/Receive Shift register. When all 8 bits have been
received, the SSP interrupt flag bit will be set and if
enabled, will wake the device from Sleep.
Note:
SSPSR must be reinitialized by writing to
the SSPBUF register before the data can
be clocked out of the slave again.
SSPSR must be reinitialized by writing to
the SSPBUF register before the data can
be clocked out of the slave again.
Sleep in Slave Mode
bit 7
bit 7
DS41418A-page 163
bit 0
bit 0