PIC16F1947-E/MR Microchip Technology, PIC16F1947-E/MR Datasheet - Page 278
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PIC16F1947-E/MR
Manufacturer Part Number
PIC16F1947-E/MR
Description
28KB Flash, 1KB RAM, 256B EEPROM, LCD, 1.8-5.5V 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16LF1933-ISS.pdf
(46 pages)
3.PIC16LF1946-IPT.pdf
(448 pages)
4.PIC16LF1946-IPT.pdf
(6 pages)
5.PIC16F1946-IPT.pdf
(8 pages)
Specifications of PIC16F1947-E/MR
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
28KB (16K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
MI2C, SPI, EUSART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
54
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 17 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F722-ISS PDF datasheet
- PIC16LF1933-ISS PDF datasheet #2
- PIC16LF1946-IPT PDF datasheet #3
- PIC16LF1946-IPT PDF datasheet #4
- PIC16F1946-IPT PDF datasheet #5
- Current page: 278 of 448
- Download datasheet (4Mb)
PIC16F/LF1946/47
24.6.6
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPxBUF register. This action will
set the Buffer Full flag bit, BF, and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDAx pin after the falling edge of SCLx is
asserted. SCLx is held low for one Baud Rate Genera-
tor rollover count (T
SCLx is released high. When the SCLx pin is released
high, it is held that way for T
pin must remain stable for that duration and some hold
time after the next falling edge of SCLx. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDAx.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received prop-
erly. The status of ACK is written into the ACKSTAT bit
on the rising edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPxIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPxBUF, leaving SCLx low and
SDAx unchanged
After the write to the SSPxBUF, each bit of the address
will be shifted out on the falling edge of SCLx until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
release the SDAx pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDAx pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT Status bit of the
SSPxCON2 register. Following the falling edge of the
ninth clock transmission of the address, the SSPxIF is
set, the BF flag is cleared and the Baud Rate Generator
is turned off until another write to the SSPxBUF takes
place, holding SCLx low and allowing SDAx to float.
24.6.6.1
In Transmit mode, the BF bit of the SSPxSTAT register
is set when the CPU writes to SSPxBUF and is cleared
when all 8 bits are shifted out.
24.6.6.2
If the user writes the SSPxBUF when a transmit is
already in progress (i.e., SSPxSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared by software before the next
transmission.
DS41414B-page 278
I
2
C MASTER MODE TRANSMISSION
BF Status Flag
WCOL Status Flag
(Figure
BRG
). Data should be valid before
24-27).
BRG
. The data on the SDAx
Preliminary
24.6.6.3
In Transmit mode, the ACKSTAT bit of the SSPxCON2
register is cleared when the slave has sent an Acknowl-
edge (ACK = 0) and is set when the slave does not
Acknowledge (ACK = 1). A slave sends an Acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
24.6.6.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Data is shifted out the SDAx pin until all 8 bits
11. The MSSPx module shifts in the ACK bit from
12. Steps 8-11 are repeated for all transmitted data
13. The user generates a Stop or Restart condition
The user generates a Start condition by setting
the SEN bit of the SSPxCON2 register.
SSPxIF is set by hardware on completion of the
Start.
SSPxIF is cleared by software.
The MSSPx module will wait the required start
time before any other operation takes place.
The user loads the SSPxBUF with the slave
address to transmit.
Address is shifted out the SDAx pin until all 8 bits
are transmitted. Transmission begins as soon
as SSPxBUF is written to.
The MSSPx module shifts in the ACK bit from
the slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
The MSSPx module generates an interrupt at
the end of the ninth clock cycle by setting the
SSPxIF bit.
The user loads the SSPxBUF with eight bits of
data.
are transmitted.
the slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
bytes.
by setting the PEN or RSEN bits of the
SSPxCON2 register. Interrupt is generated once
the Stop/Restart condition is complete.
Typical transmit sequence:
ACKSTAT Status Flag
2010 Microchip Technology Inc.
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