PIC12F617T-I/MF Microchip Technology, PIC12F617T-I/MF Datasheet - Page 119
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PIC12F617T-I/MF
Manufacturer Part Number
PIC12F617T-I/MF
Description
3.5KB Self Read/Write Flash, 128B RAM, 6 I/O, 8MHz Internal Oscillator 8 DFN 3x3
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F609T-ISN.pdf
(212 pages)
2.PIC12F609T-ISN.pdf
(8 pages)
3.PIC12F617-IP.pdf
(4 pages)
Specifications of PIC12F617T-I/MF
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12F617T-I/MF
Manufacturer:
MICROCHIP
Quantity:
1 200
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12.4.2
An overflow (FFh 00h) in the TMR0 register will set
the T0IF bit of the INTCON register. The interrupt can
be enabled/disabled by setting/clearing T0IE bit of the
INTCON register. See Section 6.0 “Timer0 Module”
for operation of the Timer0 module.
FIGURE 12-7:
2010 Microchip Technology Inc.
(615/617
(615/617 only)
(615/617 only)
only)
TIMER0 INTERRUPT
IOC-GP0
IOC-GP1
IOC-GP2
IOC-GP3
IOC-GP4
IOC-GP5
TMR2IF
TMR2IE
TMR1IE
TMR1IF
CCP1IF
CCP1IE
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
ADIF
ADIE
CMIF
CMIE
INTERRUPT LOGIC
PIC12F609/615/617/12HV609/615
Note 1:
GPIE
GPIF
INTF
INTE
PEIE
T0IF
T0IE
GIE
Some peripherals depend upon the system clock for
operation. Since the system clock is suspended during Sleep, only
those peripherals which do not depend upon the system clock will wake
the part from Sleep. See Section 12.7.1 “Wake-up from Sleep”.
12.4.3
An input change on GPIO sets the GPIF bit of the
INTCON register. The interrupt can be enabled/
disabled by setting/clearing the GPIE bit of the
INTCON register. Plus, individual pins can be
configured through the IOC register.
Note:
GPIO INTERRUPT-ON-CHANGE
If a change on the I/O pin should occur
when any GPIO operation is being
executed, then the GPIF interrupt flag may
not get set.
Wake-up (If in Sleep mode)
Interrupt to CPU
DS41302D-page 119
(1)
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