PIC12F609T-I/MF Microchip Technology, PIC12F609T-I/MF Datasheet - Page 24
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PIC12F609T-I/MF
Manufacturer Part Number
PIC12F609T-I/MF
Description
1.75KB Flash, 64B RAM, 6 I/O, 8MHz Internal Oscillator 8 DFN 3x3mm T/R
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F609T-ISN.pdf
(212 pages)
2.PIC12F609T-ISN.pdf
(8 pages)
3.PIC12F609T-ISN.pdf
(26 pages)
4.PIC12F609T-ISN.pdf
(8 pages)
Specifications of PIC12F609T-I/MF
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFN
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC12F609T-ISN PDF datasheet
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PIC12F609/615/617/12HV609/615
2.2.2.7
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. For this device, the
P1A, P1B and Timer1 Gate functions can be moved
between different pins.
The APFCON register bits are shown in Register 2-7.
REGISTER 2-7:
DS41302D-page 24
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3-2
bit 1
bit 0
Note 1: PIC12F615/617/HV615 only.
U-0
—
2: Alternate pin function.
APFCON Register
(PIC12F615/617/HV615 only)
Unimplemented: Read as ‘0’
T1GSEL: TMR1 Input Pin Select bit
1 = T1G function is on GP3/T1G
0 = T1G function is on GP4/AN3/CIN1-/T1G/P1B
Unimplemented: Read as ‘0’
P1BSEL: P1B Output Pin Select bit
1 = P1B function is on GP4/AN3/CIN1-/T1G/P1B
0 = P1B function is on GP0/AN0/CIN+/P1B/ICSPDAT
P1ASEL: P1A Output Pin Select bit
1 = P1A function is on GP5/T1CKI/P1A
0 = P1A function is on GP2/AN2/T0CKI/INT/COUT/CCP1/P1A
U-0
—
APFCON:ALTERNATE PIN FUNCTION REGISTER
W = Writable bit
‘1’ = Bit is set
U-0
—
T1GSEL
R/W-0
(2)
/MCLR/V
(2)
/OSC1/CLKIN
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PP
U-0
—
(2)
(2)
/OSC2/CLKOUT
/OSC2/CLKOUT
U-0
—
(1)
2010 Microchip Technology Inc.
x = Bit is unknown
P1BSEL
R/W-0
P1ASEL
R/W-0
bit 0
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