PIC12F609-E/MF Microchip Technology, PIC12F609-E/MF Datasheet - Page 94

• Manufacturer Part Number: PIC12F609-E/MF
• Description: 1.75KB Flash, 64B RAM, 6 I/O, 8MHz Internal Oscillator 8 DFN 3x3mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F609-E/MF

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: FLASH
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFN
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC12F609/615/617/12HV609/615
11.3
The PWM mode generates a Pulse-Width Modulated
signal on the CCP1 pin. The duty cycle, period and
resolution are determined by the following registers:
• PR2
• T2CON
• CCPR1L
• CCP1CON
In Pulse-Width Modulation (PWM) mode, the CCP
module produces up to a 10-bit resolution PWM output
on the CCP1 pin. Since the CCP1 pin is multiplexed
with the PORT data latch, the TRIS for that pin must be
cleared to enable the CCP1 pin output driver.
Figure 11-3 shows a simplified block diagram of PWM
operation.
Figure 11-4 shows a typical waveform of the PWM
signal.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 11.3.7
“Setup for PWM Operation”.
FIGURE 11-3:
DS41302D-page 94
Note 1:
Note:
CCPR1H
Duty Cycle Registers
Comparator
2:
CCPR1L
PWM Mode
PR2
TMR2
Comparator
Clearing the CCP1CON register will
relinquish CCP1 control of the CCP1 pin.
The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (F
2 bits of the prescaler, to create the 10-bit time
base.
In PWM mode, CCPR1H is a read-only register.
(2)
(Slave)
(1)
SIMPLIFIED PWM BLOCK
DIAGRAM
Clear Timer2,
toggle CCP1 pin and
latch duty cycle
CCP1CON<5:4>
S
R
Q
TRIS
OSC
CCP1
), or
The PWM output (Figure 11-4) has a time base
(period) and a time that the output stays high (duty
cycle).
FIGURE 11-4:
Pulse Width
TMR2 = 0
Period
CCP PWM OUTPUT
TMR2 = CCPRxL:CCPxCON<5:4>
 2010 Microchip Technology Inc.
TMR2 = PR2