MCP3903T-E/SS Microchip Technology, MCP3903T-E/SS Datasheet - Page 20

• Manufacturer Part Number: MCP3903T-E/SS
• Description: Six Channel Energy Meter Front End, SPI Interface 28 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP3903T-E/SS

• Number Of Bits: 24
• Number Of Channels: 6
• Power (watts): -
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 3.6 V
• Package / Case: 28-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP3903
4.13
The MCP3903 incorporates six Delta-Sigma ADCs with
a multi-bit digital to analog converter as quantizer. A
Delta-Sigma ADC is an oversampling converter that
incorporates a built-in modulator which is digitizing the
quantity of charge integrated by the modulator loop
(see
forming the analog-to-digital conversion. The quantizer
is typically 1-bit, or a simple comparator which helps to
maintain the linearity performance of the ADC (the
DAC structure is inherently linear in this case).
Multi-bit quantizers help to lower the quantization error
(the error fed back in the loop can be very large with
1-bit quantizers) without changing the order of the
modulator or the OSR, which leads to better SNR
figures. However, typically, the linearity of such
architectures is more difficult to achieve since the DAC
is no more simple to realize and its linearity limits the
THD of such ADCs.
The MCP3903’s 5-level quantizer is a flash ADC
composed of 4 comparators arranged with equally
spaced thresholds and a thermometer coding. The
MCP3903 also includes proprietary 5-level DAC
architecture that is inherently linear for improved THD
figures.
4.14
A Delta-Sigma converter is an integrating converter. It
also has a finite quantization step (LSB) which can be
detected by its quantizer. A DC input voltage that is
below the quantization step should only provide an all
zeros result since the input is not large enough to be
detected. As an integrating device, any Delta-Sigma
will show, in this case, idle tones. This means that the
output will have spurs in the frequency content that are
depending on the ratio between quantization step
voltage and the input voltage. These spurs are the
result of the integrated sub-quantization step inputs
that will eventually cross the quantization steps after a
long enough integration. This will induce an AC
frequency at the output of the ADC and can be shown
in the ADC output spectrum.
These idle tones are residues that are inherent to the
quantization process and the fact that the converter is
integrating at all times without being reset. They are
residues of the finite resolution of the conversion
process. They are very difficult to attenuate and they
are heavily signal dependent. They can degrade both
SFDR and THD of the converter, even for DC inputs.
They can be localized in the baseband of the converter
and thus difficult to filter from the actual input signal.
DS25048B-page 20
Figure
MCP3903 Delta-Sigma
Architecture
Idle Tones
5-1). The quantizer is the block that is per-
For power metering applications, idle tones can be very
disturbing because energy can be detected even at the
50 or 60 Hz frequency, depending on the DC offset of
the ADCs, while no power is really present at the
inputs. The only practical way to suppress or attenuate
idle tones phenomenon is to apply dithering to the
ADC. The idle tones amplitudes are a function of the
order of the modulator, the OSR and the number of
levels in the quantizer of the modulator. A higher order,
a higher OSR, or a higher number of levels for the
quantizer will attenuate the idle tones amplitude.
4.15
In order to suppress or attenuate the idle tones present
in any Delta-Sigma ADCs, dithering can be applied to
the ADC. Dithering is the process of adding an error to
the ADC feedback loop in order to “decorrelate” the
outputs and “break” the idle tone’s behavior. Usually a
random or pseudo-random generator adds an analog
or digital error to the feedback loop of the delta-sigma
ADC in order to ensure that no tonal behavior can
happen at its outputs. This error is filter by the feedback
loop and typically has a zero average value so that the
converter static transfer function is not disturbed by the
dithering process. However, the dithering process
slightly increases the noise floor (it adds noise to the
part) while reducing its tonal behavior and thus
improving SFDR and THD. The dithering process
scrambles the idle tones into baseband white noise and
ensures that dynamic specs (SNR, SINAD, THD,
SFDR) are less signal dependent. The MCP3903
incorporates a proprietary dithering algorithm on all
ADCs in order to remove idle tones and improve THD,
which is crucial for power metering applications.
Dithering
© 2011 Microchip Technology Inc.