MCP2200T-I/MQ Microchip Technology, MCP2200T-I/MQ Datasheet - Page 9

• Manufacturer Part Number: MCP2200T-I/MQ
• Description: USB 2.0 To UART Protocol Converter With GPIO 20 QFN 5x5x0.9mm T/R
• Manufacturer: Microchip Technology

Specifications of MCP2200T-I/MQ

• Features: USB to UART
• Number Of Channels: 8
• Fifo's: 256 Byte
• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 5.5 V
• With Auto Flow Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 20-VQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 1-2:
1.5.5
The Transmit Data Input pin has an internal pull-up.
The LIN pin is low (dominant) when T
(recessive) when T
For extra bus security, T
whenever the transmitter is disabled regardless of
external T
1.5.5.1
If T
the LBUS pin is switched to recessive mode and the
part enters TOFF Mode. This is to prevent the LIN node
from permanently driving the LIN Bus dominant. The
transmitter is re-enabled on T
1.5.6
This is the Ground pin.
1.5.7
The bidirectional LIN Bus pin (L
T
output. To reduce EMI, the edges during the signal
changes are slope controlled and include corner
rounding control for both falling and rising edges.
The internal LIN receiver observes the activities on the
LIN bus, and matches the output signal R
the state of the L
 2010 Microchip Technology Inc.
Legend: x = don’t care
Note 1:
XD
T
In
H
H
L
L
XD
x
x
XD
input. L
is driven low longer than approximately 10ms,
XD
R
Out
H
H
The FAULT/TXE is valid after approximately 25 µs after T
reporting during bus propagation delays.
L
L
TRANSMIT DATA INPUT (T
GROUND (V
LIN BUS (L
XD
x
x
BUS
voltage.
T
XD
BUS
has a current limited open collector
FAULT/TXE TRUTH TABLE
Dominant Timeout
LIN
XD
GND
GND
V
V
V
V
I/O
pin.
BB
BB
BB
BB
BUS
is high.
BUS
XD
SS
)
)
is internally forced to ‘1’
XD
Override
Thermal
BUS
OFF
OFF
OFF
OFF
rising edge.
ON
x
) is controlled by the
XD
is low, and high
XD
XD
External
to follow
Input
)
H
H
H
H
H
L
FAULT/TXE
Output
Driven
H
H
H
L
L
x
1.5.7.1
The Bus Dominant Timer is an internal timer that deac-
tivates the L
25 milliseconds of dominant state on the L
timer is reset on any recessive L
The LIN bus transmitter will be re-enabled after a
recessive state on the L
Disabling can be caused by the LIN bus being
externally held dominant, or by T
Additionally, on the MCP2004, the FAULT pin will be
driven low to indicate the Transmitter Off state.
1.5.8
This is the Battery Positive Supply Voltage pin.
1.5.9
This is the External Voltage Regulator Enable pin.
Open source output is pulled high to V
except Power Down.
1.5.10
Do not electrically connect, or connect to Vss.
XD
FAULT, T
(Note 1)
OK
OK
OK, data is being received from the LIN
FAULT, Transceiver in thermal shutdown
NO FAULT, the CPU is commanding the
transceiver to turn off the transmitter driver
falling edge. This is to eliminate false fault
BATTERY (V
VOLTAGE REGULATOR ENABLE
OUTPUT (V
EXPOSED THERMAL PAD (EP)
Bus Dominant Timer
BUS
XD
driven low, LIN
transmitter after approximately
BUS
MCP2003/4
REN
Definition
BB
pin as long as CS is high.
)
)
BUS
XD
BUS
state.
being driven low.
DS22230C-page 9
shorted to V
BB
in all modes,
BUS
pin. The
BUS
BB