MC33989PEG Freescale Semiconductor, MC33989PEG Datasheet - Page 26

• Manufacturer Part Number: MC33989PEG
• Description: SBC-HS
• Manufacturer: Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION
RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS
SPI WAKE-UP
high level. In Stop mode, this corresponds with the condition where the MCU and SBC are in Stop mode; and when the
application wake-up event comes through the MCU.
DEVICE POWER-UP, SBC WAKE-UP
Normal Request mode.
DEBUG MODE: HARDWARE AND SOFTWARE DEBUG WITH THE SBC
SBC dedicated routine must be debugged. The following features allow debug of the software by allowing the possibility of
disabling the SBC internal software Watchdog timer.
DEVICE POWER-UP, RESET PIN CONNECTED TO VDD1
every 350 ms. In order to allow software debug and avoid MCU reset, the Reset pin can be connected directly to VDD1 by a
jumper.
DEBUG MODES WITH SOFTWARE WATCHDOG DISABLED THOUGH SPI (NORMAL DEBUG, STANDBY
AND STOP DEBUG)
Watchdog during SBC normal operation, the watchdog disable must be achieved the following sequence:
• Step 1–Power down the SBC
• Step 2–Power-up the SBC (The BATFAIL bit is set, allowing the SBC to enter Normal Request mode)
• Step 3–Write to TIM1 register allowing SBC entering Normal mode
• Step 4–Write to MCR register with data 0000, enabling the Debug mode. Complete SPI byte: 000 1 0000
• Step 5–Write to MCR register normal debug (0001x101)
• Step 6–To leave the Debug mode, write 0000 to MCR register
hardware debug.
period of the Normal Request mode. If this step is not accomplished in a timely manner, the SBC will go into Reset mode, entering
Normal Request again.
Request mode for a time period of 350 ms. To avoid the SBC generating a reset (enter Reset mode) the desired next Debug
mode (Normal Debug or Standby Debug) should be configured within the 350 ms time period of the Normal Request mode. For
details, please refer to State Machine in Debug mode,
illustrates the Debug mode enter.
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The device can wake-up by the CS pin in Sleep or Stop modes. Wake-up is detected by the CS pin transition from low to a
After device or system power-up, or after the SBC wakes up from Sleep mode, it enters into Reset mode prior to moving into
When the SBC is mounted on the same printed circuit board as the microcontroller it supplies, both application software and
At SBC power-up the V
The Watchdog software can be disabled through SPI. To avoid unwanted watchdog disable while limiting the risk of disabling
While in Debug mode, the SBC can be used without having to clear the WD on a regular basis to facilitate software and
At Step 2, the SBC is in Normal Request. Steps 3, 4, and 5 should be completed consecutively and within the 350 ms time
When the SBC is in Debug mode, and set in Stop Debug or Sleep Debug, when a wake-up occurs the SBC enters Normal
To avoid entering Debug mode after a power-up, first read BATFAIL bit (MCR read) and write 0000 into MCR.
Debug Mode
Batfail
VDD1
VSUP
SPI
TIM1(Step 3)
DD1
MCR(Step4)
voltage is provided, but if no SPI communication occurs to configure the device, a reset occurs
MCR (Step5)
Figure 11. Debug Mode Enter
SPI: Read Batfail
SBC in Debug Mode, No WD
Figure
16.
MCR (Step6)
SBC Not in Debug Mode and WD ON
Analog Integrated Circuit Device Data
Freescale Semiconductor
Figure 15