XC5VLX50T-1FFG665C Xilinx Inc, XC5VLX50T-1FFG665C Datasheet - Page 213
![FPGA, VIRTEX-5 LXT, 50K, 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50T-1FFG665C
Manufacturer Part Number
XC5VLX50T-1FFG665C
Description
FPGA, VIRTEX-5 LXT, 50K, 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FFG665C
No. Of Logic Blocks
7200
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
2211840
No. Of I/o's
360
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1565
Available stocks
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Quantity:
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Shift Registers (SRLs) Primitive
Port Signals
Inverting Clock Pins
The clock pin (CLK) has an individual inversion option. The clock signal can be active at
the negative edge of the clock or the positive edge for the clock without requiring other
logic resources. The default is at the positive clock edge
Global Set/Reset – GSR
The global set/reset (GSR) signal does not affect distributed RAM modules.
One primitive is available for the 32-bit shift register (SRLC32E).
32-bit shift register primitive.
X-Ref Target - Figure 5-33
Instantiating several 32-bit shift register with dedicated multiplexers (F7AMUX, F7BMUX,
and F8MUX) allows a cascadable shift register chain of up to 128-bit in a slice.
through
document illustrate the various implementation of cascadable shift registers greater than
32 bits.
Clock – CLK
Either the rising edge or the falling edge of the clock is used for the synchronous shift
operation. The data and clock enable input pins have setup times referenced to the chosen
edge of CLK.
Data In – D
The data input provides new data (one bit) to be shifted into the shift register.
Clock Enable - CE
The clock enable pin affects shift functionality. An inactive clock enable pin does not shift
data into the shift register and does not write new data. Activating the clock enable allows
the data in (D) to be written to the first location and all data to be shifted by one location.
When available, new data appears on output pins (Q) and the cascadable output pin (Q31).
Address – A[4:0]
The address input selects the bit (range 0 to 31) to be read. The nth bit is available on the
output pin (Q). Address inputs have no effect on the cascadable output pin (Q31). It is
always the last bit of the shift register (bit 31).
Figure 5-20
in the
www.xilinx.com
Shift Registers (Available in SLICEM only)
Figure 5-33: 32-bit Shift Register
6
SRLC32E
D
A[4:0]
CE
CLK
UG190_5_33_050506
Q31
Q
Figure 5-33
section of this
CLB Primitives
shows the
Figure 5-18
213
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