MCP4725A2T-E/CH Microchip Technology, MCP4725A2T-E/CH Datasheet - Page 28

• Manufacturer Part Number: MCP4725A2T-E/CH
• Description: DAC 1-CH Resistor-String 12-Bit 6-Pin SOT-23 T/R
• Manufacturer: Microchip Technology

Specifications of MCP4725A2T-E/CH

• Package: 6SOT-23
• Resolution: 12 Bit
• Architecture: Resistor-String
• Digital Interface Type: Serial (2-Wire, I2C)
• Number Of Outputs Per Chip: 1
• Output Type: Voltage
• Full Scale Error: ±2 %FSR
• Integral Nonlinearity Error: ±14.5 LSB
• Maximum Settling Time: 6(Typ) us
• Settling Time: 6µs
• Number Of Bits: 12
• Data Interface: I²C, Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCP4725DM-PTPLS - BOARD DAUGHTER PICTAIL MCP4725
• Power Dissipation (max): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MCP4725A2T-E/CH; MCP4725A2T-E/CHTR

MCP4725
7.3
The MCP4725 device acknowledges the general call
address (0x00 in the first byte). The meaning of the
general call address is always specified in the second
byte (see
allow to use “00000000” (00h) in the second byte.
Please refer to the Phillips I
details of the General Call specifications. The
MCP4725 supports the following general calls:
7.3.1
The general reset occurs if the second byte is
“00000110” (06h). At the acknowledgement of this
byte, the device will abort current conversion and
perform an internal reset similar to a power-on-reset
(POR). Immediately after this reset event, the device
uploads the contents of the EEPROM into the DAC
register.
7.3.2
If the second byte is “00001001” (09h), the device will
reset the power-down bits. After receiving this com-
mand, the power-down bits of the DAC register are set
to a normal operation (PD1, PD2 = 0,0). The power-
down bit settings in EEPROM are not affected.
FIGURE 7-2:
Format.
7.4
The I
device must be ‘activated’ to operate in high-speed
(3.4 Mbit/s) mode. This is done by sending a special
address byte of 00001XXX following the START bit.
The XXX bits are unique to the high-speed (HS) mode
Master. This byte is referred to as the high-speed (HS)
Master Mode Code (HSMMC). The MCP4725 device
does not acknowledge this byte. However, upon
receiving this command, the device switches to HS
mode and can communicate at up to 3.4 Mbit/s on SDA
and SCL lines. The device will switch out of the HS
mode on the next STOP condition.
For more information on the HS mode, or other I
modes, please refer to the Phillips I
DS22039D-page 28
0 0 0 0 0 0 0 0 A
(General Call Address
2
C specification requires that a high-speed mode
General Call
High-Speed (HS) Mode
First Byte
Figure
GENERAL CALL RESET
GENERAL CALL WAKE-UP
7-2). The I
ACK
General Call Address
)
2
x
C specification does not
2
C document for more
x
x x x x x x
Second Byte
2
C specification.
LSB
ACK
A
2
C
7.5
The I
protocol:
• Data transfer may be initiated only when the bus
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined using
7.5.1
Both data and clock lines remain HIGH.
7.5.2
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START
condition.
7.5.3
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
7.5.4
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition.
is not busy.
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
2
C specification defines the following bus
I
2
C BUS CHARACTERISTICS
BUS NOT BUSY (A)
START DATA TRANSFER (B)
STOP DATA TRANSFER (C)
DATA VALID (D)
Figure
7-3.
© 2009 Microchip Technology Inc.