PEB4266VV12XT Infineon Technologies, PEB4266VV12XT Datasheet - Page 177
PEB4266VV12XT
Manufacturer Part Number
PEB4266VV12XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEB4266VV12XT.pdf
(383 pages)
Specifications of PEB4266VV12XT
On-hook Transmission
Yes
Polarity Reversal
Yes
On-chip Ring Relay Driver
Yes
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Pin Count
22
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Preliminary
Bit
After a hardware reset the RSTAT bit is set and generates an interrupt. Therefore the
default value of INTREG2 is 20h. After reading all four interrupt registers, the INTREG2
value changes to 4Fh.
LM-THRES
READY
RSTAT
LM-OK
IO[4:1]-DU
Data Sheet
08
H
INTREG2
THRES
LM-
7
Data on IO pins 1 to 4 filtered by DUP-IO counter and interrupt generation
masked by the IO[4:1]-DU-M bits. A change of any of this bits generates
an interrupt.
Reset status since last interrupt.
RSTAT = 0
RSTAT = 1
Level metering sequence has finished. An interrupt is only generated if
the LM-OK bit changes from 0 to 1.
LM-OK = 0
LM-OK = 1
Indication whether the level metering result is above or below the
threshold set by the CRAM coefficients
LM-THRES = 0 Level metering result is below threshold.
LM-THRES = 1 Level metering result is above threshold.
Indication whether the ramp generator has finished. An interrupt is only
generated if the READY bit changes from 0 to 1. Upon a new start of the
ramp generator, the bit is set to 0. For further information regarding soft
reversal see
READY = 0
READY = 1
READY RSTAT
6
Interrupt Register 2 (read-only)
Chapter
Ramp generator active.
Ramp generator not active.
No reset has occurred since the last interrupt.
Reset has occurred since the last interrupt.
Level metering result not ready.
Level metering result ready.
5
SLICOFI-2x Command Structure and Programming
3.7.2.1.
LM-OK
4
177
3
2
IO[4:1]-DU
20
DuSLIC-E/-E2/-P
H
1
2000-07-14
0
Y
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