STLC3065Q STMicroelectronics, STLC3065Q Datasheet - Page 4

• Manufacturer Part Number: STLC3065Q
• Manufacturer: STMicroelectronics

Specifications of STLC3065Q

• Number Of Channels: 1
• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Pin Count: 44
• Mounting: Surface Mount
• Operating Supply Voltage (min): 5.5V
• Lead Free Status / RoHS Status: Not Compliant

STLC3065
PIN DESCRIPTION (continued)
FUNCTIONAL DESCRIPTION
The STLC3065 is a device specifically developed
for WLL application.
It is based on a SLIC core, on purpose optimised
for this application, with the addition of a DC/DC
converter controller and a dual port in order to ful-
fil the WLL requirements.
The SLIC core performs the standard feeding,
signalling and transmission functions.
It can be set in three different operating modes
via the D0, D1, D2 pins of the control logic inter-
face (0 to 3.3V logic levels). The loop status is
carried out on the DET pin (active low).The DET
pin is an open drain output to allow easy interfac-
ing with both 3.3V and 5V logic levels.
The three possible SLIC core operating modes
are:
4/27
38,39,
Power Down (PWD)
35
23
21
22
24
33
12
13
10
11
44
40
N.
1
2
3
4
5
8
6
7
9
RSENSE
CKTTX
CTTX1
CTTX2
VBAT1
Name
GATE
CSVR
VBAT
RTTX
DET1
DET2
FTTX
DET
CLK
NC
VF
D0
D1
D2
P1
P2
Regulated battery voltage self generated by the device via DC/DC converter. Must be shorted
to VBAT1.
Driver for external Power MOS transistor.
Feedback input for DC/DC converter controller.
Power Switch Controller Clock (typ. 125KHz). From version marked STLC3065 A5, this pin
can also be connected to CVCC or AGND. When the CLK pin is connected to CVCC an
internal auto-oscillation is internally generated and it is used instead of the external clock.
When the CLK pin is connected to AGND, the GATE output is disabled.
Voltage input for current sensing. RSENSE should be connected close to this pin and VPOS
pin. The PCB layout should minimize the extra resistance introduced by the copper tracks.
Control Interface: input bit 0.
Control Interface: input bit 1.
Control interface: input bit 2.
Control Interface: port 1 selection bit
Control Interface: port 2 selection bit
Logic interface output of the supervision detector (active low).
Logic interface output of thr linr port 1 detector (active low)
Logic interface output of thr linr port 2 detector (active low)
Battery supply filter capacitor.
Metering pulse cancellation buffer output. TTX filter network should be connected to this point.
If not used should be left open.
Metering pulse buffer input this signal is sent to the line and used to perform TTX filtering.
Metering burst shaping external capacitor.
Metering burst shaping external capacitor.
Metering pulse clock input (12 KHz or 16KHz square wave).
Frame connection. Must be shorted to VBAT.
Not connected.
Table 1 shows how to set the different SLIC core
operating modes.
Table 1. SLIC core operating modes.
D0
Active
Ringing
0
0
0
1
1
1
Function
D1
0
1
1
1
1
0
0/1
D2
X
0
1
0
1
Power Down
Active Normal Polarity
Active Reverse Polarity
Active TTX injection (N.P.)
Active TTX injection (R.P.)
Ring (D2 bit toggles @ fring)
Operating Mode