SI3210M-E-FMR Silicon Laboratories Inc, SI3210M-E-FMR Datasheet - Page 121
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SI3210M-E-FMR
Manufacturer Part Number
SI3210M-E-FMR
Description
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI3210M-E-FMR.pdf
(138 pages)
Specifications of SI3210M-E-FMR
Lead Free Status / RoHS Status
Supplier Unconfirmed
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4.3. Digital Programmable Gain/Attenua-
See
programmable
computing register values. All values are represented in
2s-complement format.
Note: The values of all indirect registers are undefined follow-
Addr.
Addr.
26
27
26
27
tion
ing the reset state. Shaded areas denote bits that can
be read and written but should be written to zeroes.
functional
Receive Path Digital to Analog Converter Gain/Attenuation.
This register sets gain/attenuation for the receive path. The digitized signal is effectively mul-
tiplied by DACG to achieve gain/attenuation. A value of 0x00 corresponds to – dB gain
(mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain
of 6 dB.
Transmit Path Analog to Digital Converter Gain/Attenuation.
This register sets gain/attenuation for the transmit path. The digitized signal is effectively
multiplied by ADCG to achieve gain/attenuation. A value of 0x00 corresponds to – dB gain
(mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain
of 6 dB.
D15
Table 42. Digital Programmable Gain/Attenuation Indirect Registers Description
Table 41. Digital Programmable Gain/Attenuation Indirect Registers Summary
D14
gain/attenuation
description
D13
D12
sections
for
D11
guidelines
DACG[11:0]
ADCG[11:0]
D10
of
Description
D9
digital
Rev. 1.45
on
D8
D7
D6
D5
Si3210/Si3211
D4
D3
D2
Reference
D1
Page
48
48
D0
121
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