SI3210M-KTR Silicon Laboratories Inc, SI3210M-KTR Datasheet
SI3210M-KTR
Specifications of SI3210M-KTR
Related parts for SI3210M-KTR
SI3210M-KTR Summary of contents
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P SLIC P RO ROGRAMMABLE INGING Features 100% programmable global solution Performs all BORSCHT functions DC-DC controller provides tracking battery from a 3.3–35V input ...
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Si3210/Si3211 T C ABLE O F ONTENTS 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information Parameter DC Supply Voltage Input Current, Digital Input Pins Digital Input Voltage 2 Operating Temperature Range Storage Temperature Range TSSOP-38 Thermal Resistance, Typical QFN-38 Thermal Resistance, Typical 2 Continuous ...
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Si3210/Si3211 Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Si3210/11 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal ...
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Table 3. AC Characteristics (Continued 3. °C for F-Grade, – °C for G-Grade) DDA DDD A Parameter 2-Wire Return Loss Transhybrid Balance 4 Idle Channel Noise ...
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Si3210/Si3211 Figure 1. Transmit and Receive Path SNDR Fundamental Output Power (dBm0) Figure 2. Overload Compression Performance 2 Fundamental Input Power (dBm0) Rev. ...
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Typical Response Figure 3. Transmit Path Frequency Response Rev. 1.5 Si3210/Si3211 Typical Response 7 ...
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Si3210/Si3211 Figure 4. Receive Path Frequency Response 8 Rev. 1.5 ...
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Figure 5. Transmit Group Delay Distortion Figure 6. Receive Group Delay Distortion Rev. 1.5 Si3210/Si3211 9 ...
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Si3210/Si3211 Table 4. Linefeed Characteristics ( 3. 70°C for F-Grade, –40 to 85°C for G-Grade) DDA DDD A Parameter Symbol Loop Resistance Range* R LOOP DC Loop Current Accuracy DC ...
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Table 5. Monitor ADC Characteristics ( 3. °C for F-Grade, – °C for G-Grade) DDA DDD A Parameter Symbol Differential Nonlinearity DNLE (6-bit resolution) Integral Nonlinearity INLE ...
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Si3210/Si3211 Table 8. Power Supply Characteristics ( 3. °C for F-Grade, – °C for G-Grade) DDA DDD A Parameter Symbol Power Supply Current Analog and ...
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Table 9. Switching Characteristics (General Inputs 3. °C for F-Grade, – °C for G-Grade, C DDA DDA A Parameter Rise Time, RESET 2 RESET Pulse Width ...
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Si3210/Si3211 SCLK t su1 CS SDI t d1 SDO Table 11. Switching Characteristics—PCM Highway Serial Interface V = 3. °C for F-Grade, – °C for G-Grade Parameter ...
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... Guide for the SI3210 DC-DC Converter”. 2. Only one component per system needed. 3. All circuit ground should have a single-point connection to the ground plane. 4. Si3201 bottom-side exposed pad should be electrically and thermally connected to bulk ground plane. 5. Pin numbers for TSSOP shown. Figure 9. Si3210/Si3210M Application Circuit Using Si3201 ...
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... Si3210/Si3211 Table 12. Si3210/Si3210M + Si3201 External Component Values Component(s) 10 µ Ceramic Low Leakage C1,C2 Electrolytic, ±20% C3,C4 220 nF, 100 V, X7R, ±20% C5,C6 22 nF, 100 V, X7R, ±20% C15,C16,C17,C24 0.1 µ Y5V, ±20% C18,C19 4.7 µF, ceramic X7R, ±20% C26 0.1 µF, 100 V, X7R, ±20% C30,C31 10 µ ...
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SDCH 1 R19 Note 1 1 R20 SDCL C10 R16 0.1 µF 200 DCFF 2N2222 DCDRV Notes: 1. Values and configurations for these components can be derived from “AN45: Design Guide for the Si3210 DC-DC Converter” or Table 21. 2. ...
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Si3210/Si3211 Table 13. Si3210 BJT/Inductor DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20% C10 0.1 µ X7R, ±20% C14* 0.1 µF, X7R, ±20% C25* 10 µF, Electrolytic, ±20% 200 , 1/10 W, ±5% R16 ...
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... M1 IRLL014N R17 200 k DCDRV NC Notes: 1. Values and configurations for these components can be derived from AN45 or Table 20. 2. Voltage rating for C14 and C25 must be greater than VDC. Figure 11. Si3210M MOSFET/Transformer DC-DC Converter Circuit Rev. 1.5 Si3210/Si3211 VDC C25 C14 1 10 µF 0.1 µ ...
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... Si3210/Si3211 Table 14. Si3210M MOSFET/Transformer DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20% C14* 0.1 µF, X7R, ±20% C25* 10 µF, Electrolytic, ±20% C27 470 pF, 100 V, X7R, ±20% R17 200 k, 1/10 W, ±5% 1/4 W, ±5% (See “AN45: Design Guide for R18 the Si3210 DC-DC Converter” or Table 20 for value selection) 1/10 W, ± ...
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TIP TIP Protection Circuit RING RING C9 0.1 µF GND Notes: 1. Only one component per system needed. 2. All circuit grounds should have a single- point connection to the ground plane. ...
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Si3210/Si3211 Table 15. Si3211 + Si3201 External Component Values Component(s) C1,C2 10 µ Ceramic Low-Leakage Electrolytic, ±20% C3,C4 220 nF, 100 V, X7R, ±20% C5,C6 22 nF, 100 V, X7R, ±20% C9 0.1 µF, 100 ...
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... Optional components to improve idle channel noise. 5. The trace resistance between R6 and C26 should equal the trace resistance between R 7 and C26. 6. Pin numbers for TSSOP shown. Figure 13. Si3210/Si3210M Typical Application Circuit Using Discrete Components R1 200k 15 GND STIPDC 20 ...
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... Si3210/Si3211 Table 16. Si3210/Si3210M External Component Values—Discrete Solution Component(s) 10 µ Ceramic Low-Leakage C1,C2 Electrolytic, 20% 220 nF, 100 V, X7R, 20% C3,C4 22 nF, 100 V, X7R, 20% C5,C6 220 nF X7R, 20% C7,C8 0.1 µ Y5V, 20% C15,C16,C17 0.1 µF, 100 V, X7R, 20% C26 C30,C31 10 µ ...
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Q1 5401 R10 10 TIP Q6 5551 C8 C5 220nF 22nF Protection Circuit R6 C6 80.6 22nF RING C26 0.1 µF Notes: 1. Only one component per system needed. 2. All circuit grounds should have a single-point connection to the ...
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Si3210/Si3211 Table 17. Si3211 External Component Values—Discrete Solution Component(s) 10 µ Ceramic Low Leakage C1,C2 Electrolytic, 20% 220 nF, 100 V, X7R, 20% C3,C4 22 nF, 100 V, X7R, 20% C5,C6 220 nF ...
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... The subcircuit above can be substituted into any of the ProSLIC solutions as an optional bias circuit for Q5 and Q6. For this optional subcircuit, C7 and C8 differ in voltage and capacitance from the standard circuit. R23 and R24 are additional components. Table 19. Component Value Selection for Si3210/Si3210M Component 1/ resistor ...
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... Si3210/Si3211 Table 20. Component Value Selection Examples for Si3210M MOSFET/Transformer DC-DC Converter VDC Maximum Ringing Load/ Loop Resistance 3 REN/117 3 REN/117 5 REN/117 REN/117 Notes: 1. There are other system and software conditions that influence component value selection. Refer to “AN45: Design Guide for the Si3210 DC-DC Converter” for detailed guidance. ...
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Functional Description ® The ProSLIC is a single, low-voltage CMOS device that provides all the SLIC, codec, DTMF detection, and signal generation functions needed for a complete analog telephone interface. The ProSLIC performs all battery, overvoltage, ringing, supervision, codec, ...
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Si3210/Si3211 2.1.2. Linefeed Architecture The ProSLIC is a low-voltage CMOS device that uses either an Si3201 linefeed interface IC or low-cost external components to control the high voltages required for subscriber line interfaces. Figure simplified illustration of ...
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Audio Codec A/D D/A AC Control AC Sense Control Loop TIP or RING Figure 17. Simplified ProSLIC Linefeed Architecture for TIP and RING Leads (One Shown) Table 23. ProSLIC Linefeed Operations LF[2:0]* Linefeed State 000 ...
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Si3210/Si3211 Table 24. Measured Real-Time Linefeed Interface Characteristics Parameter Loop Voltage Sense (V – V TIP RING Loop Current Sense TIP Voltage Sense RING Voltage Sense Battery Voltage Sense BAT Battery Voltage Sense BAT ...
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P 1.28 7 MAX ------------------------------ - ----------------- - PPT56 = 2 = Resolution 0.0304 Table 25. Associated Power Monitoring and Power Fault Registers Parameter Power Monitor Pointer Line Power Monitor Output Power Alarm Threshold, Q1 & Q2 Power ...
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Si3210/Si3211 LCS Input ISP_OUT Signal LVS Processor LFS LCVE 2.1.6. Loop Closure Transition Detection A loop closure transition event signals that the terminal equipment has gone from on-hook to off-hook or from off- hook to on-hook; detection occurs while the ...
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Table 26. Register Set for Loop Closure Detection Parameter Register Loop Closure LCIP Interrupt Pending Loop Closure LCIE Interrupt Enable Loop Closure Thresh- LCRT[5:0] old Loop Closure LCRTL[5:0] Threshold—Lower Loop Closure Filter NCLR[12:0] Coefficient Loop Closure Detect LCR Status (monitor ...
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... DCDRV and DCFF pins to switch Q7 on and off. DCDRV controls Q7 through NPN BJT Q8. DCFF is ac-coupled to Q7 through capacitor C10 to assist R16 in turning off Q7. Therefore, DCFF must have opposite polarity to DCDRV, and the Si3210 (not Si3210M) must be used. Rev. 1.5 DCFF Signal ...
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... T1 specified in “AN45: Design Guide for the Si3210 DC-DC Converter” and includes several taps on the primary side to facilitate a wide range of input voltages. The Si3210M version of the Si3210 must be used for the application circuit depicted in Figure 11 because the DCFF pin is used to drive M1 directly and, therefore, must be the same polarity as DCDRV. DCDRV is not used in this circuit option ...
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Si3210/Si3211 The power dissipation on the NPN bipolar transistor driving the RING terminal can become large and may require a higher power rating device. The non-tracking mode of operation is required by specific terminal equipment that, in order to initiate ...
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DC-DC Converter Enhancements Silicon revisions C and higher enhancements to the dc-dc converter. The first is a multi-threshold error control algorithm that enables the dc-dc converter to adjust more quickly to voltage changes. This option is enabled by setting ...
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Si3210/Si3211 8 kHz Clock OnE Zero 16-Bit Cross OAT Modulo Logic Expire Counter OIT Expire OATn OATnE OITn OITnE *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively Figure 20. Simplified Tone Generator ...
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The cadence continues until the user clears the O1TAE and O1TIE control bits. The zero crossing detect feature can be implemented by setting the ...
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Si3210/Si3211 O1E ... ... 0 AT1 OSS1 Tone Gen. 1 Signal Output Figure 21. Tone Generator Timing Diagram 2.3.4. Enhanced FSK Waveform Generation Silicon revisions C and higher support enhanced FSK generation capabilities, which can be enabled by ...
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Table 30. Registers for Ringing Generation Parameter Ringing Waveform Ringing Voltage Offset Enable Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control (Initiates Ringing State) High Battery Voltage ...
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Si3210/Si3211 15 RCO 0.99211 2 32509 = = 1 70 0.00789 15 ----- - RNGX = -------------------- - 1.99211 RNGY addition, the user must select the ...
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N is the ringing REN load (max value = 5), REN I is the offset current flowing in the line driver circuit OS (max value = 2 mA), and V = amplitude of the ac ringing waveform. AC,PK It ...
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Si3210/Si3211 Table 31. Associated Registers for Ring Trip Detection Parameter Ring Trip Interrupt Pending Ring Trip Interrupt Enable Ring Trip Detect Debounce Interval Ring Trip Threshold Ring Trip Filter Coefficient Ring Trip Detect Status (monitor only) Note: The ProSLIC uses ...
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Table 33. Associated Pulse Metering Generator Registers Parameter Pulse Metering Frequency Coefficient Pulse Metering Amplitude Coefficient Pulse Metering Attack/Decay Ramp Rate Pulse Metering Active Timer Pulse Metering Inactive Timer Pulse Metering Control Status and control registers Note: The ProSLIC uses ...
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Si3210/Si3211 2.7. Audio Path Unlike traditional SLICs, the codec function is integrated into the ProSLIC. The 16-bit codec offers programmable gain/attenuation blocks and several loopback modes. The signal path block diagram is shown in Figure 25. 2.7.1. Transmit Path In ...
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Si3210/Si3211 Rev. 1.5 49 ...
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Si3210/Si3211 2.7.2. Receive Path In the receive path, the optionally-compressed 8-bit data is first expanded to 16-bit words. The PCMF register bit can bypass the expansion process, in which case two 8-bit words are assembled into one 16- bit word. ...
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An additional analog loopback (ALM1) takes the digital stream at the output of the A/D converter and feeds it back to the D/A converter. (See ...
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Si3210/Si3211 Pulse metering active timer expired Pulse metering inactive timer expired Indirect register access complete The interface to the interrupt logic consists of six registers. Three interrupt status registers contain one bit for each of the above ...
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SCLK CS SDI SDO SCLK CS SDI SDO High Impedance Don't Care High Impedance Figure 26. Serial Write 8-Bit Mode Don't Care ...
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Si3210/Si3211 SDO CPU CS SDI Chip Select Byte SCLK SDI0 SDI1 – SDI2 – – SDI3 – – – ...
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PCM Interface The ProSLIC contains a flexible programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled via the PCLK and FSYNC inputs as well as PCM Mode Select (direct Register 1), PCM ...
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Si3210/Si3211 PCLK FSYNC PCLK_CNT 0 1 DRX DTX HI-Z Figure 31. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10) PCLK FSYNC 0 1 PCLK_CNT DRX MSB DTX HI-Z Figure 32. GCI Example, Timeslot 1 (TXS/RXS = 0) 2.13. ...
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Table 34. µ-Law Encode-Decode Characteristics Segment #Intervals X Interval Size Number 256 128 ...
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Si3210/Si3211 Table 35. A-Law Encode-Decode Characteristics Segment #intervals X interval size Number 128 ...
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Control Registers Note: Any register not listed here is reserved and must not be written. Register Name 0 SPI Mode Select 1 PCM Mode Select 2 PCM Transmit Start Count—Low Byte 3 PCM Transmit Start Count—High Byte 4 PCM ...
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Si3210/Si3211 Table 36. Direct Register Summary (Continued) Register Name 28 Indirect Data Access— Low Byte 29 Indirect Data Access— High Byte 30 Indirect Address 31 Indirect Address Status 32 Oscillator 1 Control 33 Oscillator 2 Control 34 Ringing Oscillator Control ...
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Table 36. Direct Register Summary (Continued) Register Name 47 Pulse Metering Oscillator Inactive Timer—High Byte 48 Ringing Oscillator Active Timer—Low Byte 49 Ringing Oscillator Active Timer—High Byte 50 Ringing Oscillator Inac- tive Timer—Low Byte 51 Ringing Oscillator Inac- tive Timer—High ...
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Si3210/Si3211 Table 36. Direct Register Summary (Continued) Register Name 79 Loop Current Sense 80 TIP Voltage Sense 81 RING Voltage Sense 82 Battery Voltage Sense 1 83 Battery Voltage Sense 2 84 Transistor 1 Current Sense 85 Transistor 2 Current ...
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Table 36. Direct Register Summary (Continued) Register Name 102 Current Limit Calibration Result 103 Monitor ADC Offset Calibration Result 104 Analog DAC/ADC Offset 105 DAC Offset Calibration Result 106 Common Mode Balance Calibration Result 107 DC Peak Current Calibration Result ...
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... Enable SPI daisy chain mode. 6 SPIM SPI Mode Causes SDO to tri-state on rising edge of SCLK of LSB Normal operation; SDO tri-states on rising edge of CS. 5:4 PNI[1:0] Part Number Identification Si3210 01 = Si3211 10 = Unused 11 = Si3210M 3:0 RNI[3:0] Revision Number Identification. 0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc PNI[1:0] R Function Rev ...
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Register 1. PCM Mode Select Bit D7 D6 Name PNI2 Type Reset settings = 0000_1000 Bit Name 7 PNI2 Part Number Identification Si3210/11 family Si3215/16 family. 6 Reserved Read returns zero. 5 PCME PCM Enable. ...
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Si3210/Si3211 Register 2. PCM Transmit Start Count—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 TXS[7:0] PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following FSYNC before data trans- mission ...
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Register 5. PCM Receive Start Count—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1:0 RXS[9:8] PCM Receive Start Count. PCM receive start count equals the number of PCLKs following FSYNC ...
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Si3210/Si3211 Bit Name 7:5 Reserved Read returns zero. 4 DOUT DOUT Pin Output Data (Si3211 only DOUT pin driven low DOUT pin driven high. Si3210 = Reserved. 3 DIO2 DIO2 Pin Input/Output Direction (Si3211 only). 0 ...
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Register 8. Audio Path Loopback Control Bit D7 D6 Name Type Reset settings = 0000_0010 Bit Name 7:3 Reserved Read returns zero. 2 ALM2 Analog Loopback Mode 2. (See Figure 25 on page 49 Full analog loopback mode ...
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Si3210/Si3211 Register 9. Audio Gain Control Bit D7 D6 Name RXHP TXHP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 RXHP Receive Path High Pass Filter Disable HPF enabled in receive path, RHPF HPF ...
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Register 10. Two-Wire Impedance Synthesis Control Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:6 Reserved Read returns zero. 5:4 CLC[1:0] Line Capacitance Compensation Off ...
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Si3210/Si3211 Register 11. Hybrid Control Bit D7 D6 Name Type Reset settings = 0011_0011 Bit Name 7 Reserved Read returns zero. 6:4 HYBP[2:0] Pulse Metering Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 ...
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Register 14. Powerdown Control 1 Bit D7 D6 Name Type Reset settings = 0001_0000 Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:6 Reserved Read returns zero. 5 PMON Pulse Metering DAC Power-On Control Automatic ...
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Si3210/Si3211 Register 15. Powerdown Control 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 ADCM Analog to Digital Converter Manual/Automatic Power Control Automatic power control Manual power ...
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Register 18. Interrupt Status 1 Bit D7 D6 Name PMIP PMAP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 PMIP Pulse Metering Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt ...
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Si3210/Si3211 Register 19. Interrupt Status 2 Bit D7 D6 Name Q6AP Q5AP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AP Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt ...
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Register 20. Interrupt Status 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 CMCP Common Mode Calibration Error Interrupt. This bit is set when off-hook/on-hook status changes during the common mode ...
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Si3210/Si3211 Register 21. Interrupt Enable 1 Bit D7 D6 Name PMIE PMAE Type R/W R/W Reset settings = 0000_0000 Bit Name 7 PMIE Pulse Metering Inactive Timer Interrupt Enable Interrupt masked Interrupt enabled. 6 PMAE Pulse ...
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Register 22. Interrupt Enable 2 Bit D7 D6 Name Q6AE Q5AE Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AE Power Alarm Q6 Interrupt Enable Interrupt masked Interrupt enabled. 6 Q5AE Power Alarm Q5 ...
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Si3210/Si3211 Register 23. Interrupt Enable 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 CMCE Common Mode Calibration Error Interrupt Enable Interrupt masked Interrupt enabled. 1 INDE ...
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Register 24. DTMF Decode Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 VAL DTMF Valid Digit Decoded Not currently detecting digit Currently detecting digit. 3:0 DIG[3:0] ...
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Si3210/Si3211 Register 28. Indirect Data Access—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 IDA[7:0] Indirect Data Access—Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA ...
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Register 30. Indirect Address Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IAA[7:0] Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register ...
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Si3210/Si3211 Register 32. Oscillator 1 Control Bit D7 D6 Name OSS1 REL Type R R/W Reset settings = 0000_0000 Bit Name 7 OSS1 Oscillator 1 Signal Status Output signal inactive Output signal active. 6 REL Oscillator ...
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Register 33. Oscillator 2 Control Bit D7 D6 Name OSS2 Type R Reset settings = 0000_0000 Bit Name 7 OSS2 Oscillator 2 Signal Status Output signal inactive Output signal active. 6 Reserved Read returns zero. 5 ...
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Si3210/Si3211 Register 34. Ringing Oscillator Control Bit D7 D6 Name RSS Type R Reset settings = 0000_0000 Bit Name 7 RSS Ringing Signal Status Ringing oscillator output signal inactive Ringing oscillator output signal active. 6 Reserved ...
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Register 35. Pulse Metering Oscillator Control Bit D7 D6 Name PSTAT Type R Reset settings = 0000_0000 Bit Name 7 PSTAT Pulse Metering Signal Status Output signal inactive Output signal active. 6:5 Reserved Read returns zero. ...
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Si3210/Si3211 Register 37. Oscillator 1 Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT1[15:8] Oscillator 1 Active Timer. Register 38. Oscillator 1 Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = ...
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Register 40. Oscillator 2 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT2[7:0] Oscillator 2 Active Timer. LSB = 125 µs Register 41. Oscillator 2 Active Timer—High Byte Bit D7 D6 Name Type ...
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Si3210/Si3211 Register 43. Oscillator 2 Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT2[15:8] Oscillator 2 Inactive Timer. Register 44. Pulse Metering Oscillator Active Timer—Low Byte Bit D7 D6 Name Type Reset settings ...
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Register 46. Pulse Metering Oscillator Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 PIT[7:0] Pulse Metering Inactive Timer. LSB = 125 µs Register 47. Pulse Metering Oscillator Inactive Timer—High Byte Bit D7 D6 ...
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Si3210/Si3211 Register 49. Ringing Oscillator Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RAT[15:8] Ringing Active Timer. Register 50. Ringing Oscillator Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 ...
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Register 52. FSK Data Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. 0 FSKDAT FSK Data. When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, ...
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Si3210/Si3211 Register 64. Linefeed Control Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6:4 LFS[2:0] Linefeed Shadow. This register reflects the actual real-time linefeed state. Automatic operations may cause actual linefeed state ...
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Register 65. External Bipolar Transistor Control Bit D7 D6 Name SQH Type R/W Reset settings = 0110_0001 Bit Name 7 Reserved Read returns zero. 6 SQH Audio Squelch squelch STIPAC and SRINGAC pins squelched. 5 ...
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Si3210/Si3211 Register 66. Battery Feed Control Bit D7 D6 Name Type Reset settings = 0000_0011 Bit D7 D6 Name Type Reset settings = 0000_0110 Bit Name 7:5 Reserved Read returns zero. 4 VOV Overhead Voltage Range Increase. (Si3210 only; See ...
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Register 67. Automatic/Manual Control Bit D7 D6 Name MNCM Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 MNCM Common Mode Manual/Automatic Select Automatic control Manual control, in which TIP (forward) ...
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Si3210/Si3211 Register 68. Loop Closure/Ring Trip Detect Status Bit D7 D6 Name Type Reset settings = 0000_0100 Bit Name 7:3 Reserved Read returns zero. 2 DBIRAW Ring Trip/Loop Closure Unfiltered Output. State of this bit reflects the real-time output of ...
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Register 70. Ring Trip Detect Debounce Interval Bit D7 D6 Name Type Reset settings = 0000_1010 Bit Name 7 Reserved Read returns zero. 6:0 RTDI[6:0] Ring Trip Detect Debounce Interval. The value written to this register defines the minimum steady ...
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Si3210/Si3211 Register 72. On-Hook Line Voltage Bit D7 D6 Name VSGN Type R/W Reset settings = 0010_0000 Bit Name 7 Reserved Read returns zero. 6 VSGN On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage ...
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Register 74. High Battery Voltage Bit D7 D6 Name Type Reset settings = 0011_0010 Bit Name 7:6 Reserved Read returns zero. 5:0 VBATH[5:0] High Battery Voltage. The value written to this register sets high battery voltage. V equal to VBATL. ...
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Si3210/Si3211 Register 76. Power Monitor Pointer Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2:0 PWRMP[2:0] Power Monitor Pointer. Selects the external transistor from which to read power output. The power of ...
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Register 78. Loop Voltage Sense Bit D7 D6 Name LVSP Type R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 LVSP Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage (V ...
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Si3210/Si3211 Register 80. TIP Voltage Sense Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VTIP[7:0] TIP Voltage Sense. This register reports the real-time voltage at TIP with respect to ground. The range (0x00) ...
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Register 83. Battery Voltage Sense 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VBATS2[7:0] Battery Voltage Sense 2. This register is one of two registers that reports the real-time voltage ground. The ...
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Si3210/Si3211 Register 86. Transistor 3 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ3[7:0] Transistor 3 Current Sense. This register reports the real-time current through Q3. The range (0x00) to 9.59 ...
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Register 89. Transistor 6 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ6[7:0] Transistor 6 Current Sense. This register reports the real-time current through Q6. The range (0x00) to 80.58 mA ...
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... This read-only register bit indicates the polarity relationship of the DCFF pin to the DCDRV pin. Two versions of the Si3210 are offered to support the two relationships DCFF pin polarity is opposite of DCDRV pin (Si3210 DCFF pin polarity is same as DCDRV pin (Si3210M). Si3211 = Reserved. 4:0 DCTOF[4:0] DC-DC Converter Minimum Off Time (Si3210 only) ...
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Register 94. DC-DC Converter PWM Pulse Width Bit D7 D6 Name Type Reset settings = 0000_0000 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 DCPW[7:0] DC-DC Converter Pulse Width (Si3210 only). Pulse width of DCDRV is ...
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Si3210/Si3211 Register 96. Calibration Control/Status Register 1 Bit D7 D6 Name CAL Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 CAL Calibration Control/Status Bit. Setting this bit begins calibration of the entire system. 0 ...
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Register 97. Calibration Control/Status Register 2 Bit D7 D6 Name Type Reset settings = 0001_1111 Bit Name 7:5 Reserved Read returns zero. 4 CALM1 Monitor ADC Calibration Normal operation or calibration complete Calibration enabled or ...
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Si3210/Si3211 Register 99. TIP Gain Mismatch Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGMT[4:0] Gain Mismatch of IE Tracking Loop for TIP Current. Register 100. Differential Loop Current ...
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Register 102. Current Limit Calibration Result Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:5 Reserved Read returns zero. 3:0 CALGIL[3:0] Current Limit Calibration Result. Register 103. Monitor ADC Offset Calibration Result Bit D7 D6 Name CALMG1[3:0] ...
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Si3210/Si3211 Register 105. DAC Offset Calibration Result Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 DACOF[7:0] DAC Offset Calibration Result. Register 106. Common Mode Balance Calibration Result Bit D7 D6 Name Type Reset settings = 0010_0000 ...
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Register 108. Enhancement Enable Note: The Enhancement Enable register and associated features are available in silicon revisions C and later. Bit D7 D6 Name ILIMEN FSKEN Type R/W R/W Reset settings = 0000_0000 Bit D7 D6 Name ILIMEN FSKEN Type ...
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Si3210/Si3211 Bit Name 4 ZSEXT Impedance Internal Reference Resistor Disable. When enabled, this bit removes the internal reference resistor used to synthesize ac impedances for 600 + 2.1 µF and 900 + 2.16 µF so that an external resistor reference ...
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Indirect Registers Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. ...
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Si3210/Si3211 Table 38. DTMF Indirect Registers Description Addr. 0 DTMF Row 0 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 0 DTMF detection. If the ratio of power in row 0 to total ...
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Oscillators See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing register values. All values are represented in 2s-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded ...
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Si3210/Si3211 Table 40. Oscillator Indirect Registers Description Addr. Oscillator 1 Frequency Coefficient. 13 Sets tone generator 1 frequency. Oscillator 1 Amplitude Register. 14 Sets tone generator 1 signal amplitude. Oscillator 1 Initial Phase Register. 15 Sets initial phase of tone ...
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Digital Programmable Gain/Attenuation See functional description sections of digital programmable gain/attenuation for guidelines on computing register values. All values are represented in 2s-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas ...
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Si3210/Si3211 4.4. SLIC Control See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in 2s-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas ...
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Table 44. SLIC Control Indirect Registers Description Addr. 28 Loop Closure Threshold. Loop closure detection threshold. This register defines the upper bounds threshold if hys- teresis is enabled (direct Register 108, bit 0). The range is 0– 1.27 ...
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Si3210/Si3211 4.5. FSK Control For detailed instructions on FSK signal generation, refer to “Application Note 32: FSK Generation” (AN32). These registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108, bit 6) and ...
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Pin Descriptions: Si3210/11 QFN DTX FSYNC 2 RESET 3 SDCH/DIO1 4 SDCL/DIO2 DDA1 EPAD IREF 7 CAPP 8 QGND 9 CAPM 10 STIPDC 11 SRINGDC ...
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Si3210/Si3211 QFN TSSOP Name Pin # Pin # 5 9 SDCL/DIO2 6 10 VDDA1 7 11 IREF 8 12 CAPP 9 13 QGND 10 14 CAPM 11 15 STIPDC 12 16 SRINGDC 13 17 STIPE 14 18 SVBAT 15 19 ...
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QFN TSSOP Name Pin # Pin # 23 27 VDDA2 Analog Supply Voltage. Analog power supply for internal analog circuitry ITIPP Positive TIP Current Control. Analog current output driving Q1 ITIPN Negative TIP Current Control. Analog ...
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Si3210/Si3211 6. Pin Descriptions: Si3201 Pin # Name Input/ Output 1 TIP I — 3 RING I/O 4 VBAT — 5 VBATH — 7 GND — 8 VDD — 10 SRINGE O 11 STIPE O ...
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... DC-DC Converter Si3210-E-FM ProSLIC Si3210-E-GM ProSLIC Si3210M-E-FM ProSLIC Si3210M-E-GM ProSLIC Si3210-FT ProSLIC Si3210-GT ProSLIC Si3210M-FT ProSLIC Si3210M-GT ProSLIC Si3211-E-FT ProSLIC Si3211-E-GT ProSLIC Si3211-E-FM ProSLIC Si3211-E-GM ProSLIC Si3201-FS Linefeed Interface Si3201-GS Linefeed Interface Note: Add an “R” at the end of the device to denote tape and reel; 2500 quantity per reel. ...
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... Eval Board, Daughter Card Si3210-QFN Eval Board, Daughter Card Si3210-TSSOP Eval Board, Daughter Card Si3210-TSSOP Eval Board, Daughter Card Si3210M-TSSOP Eval Board, Daughter Card Si3210M-TSSOP Eval Board, Daughter Card Si3211-TSSOP Eval Board, Daughter Card Rev. 1.5 Linefeed Interface Discrete Si3201 Discrete ...
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Package Outlines and PCB Land Patterns 8.1. 38-Pin QFN 8.1.1. Package Outline: 38-Pin QFN Figure 33 illustrates the package details for the Si321x. Table 48 lists the values for the dimensions shown in the illustration aaa C ...
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Si3210/Si3211 Table 48. Package Diagram Dimensions Symbol aaa bbb ccc ddd Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1982. ...
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PCB Land Pattern: 38-Pin QFN Figure 34 shows the recommended land pattern for the Si3210/11 QFN-38 package. Table 49 lists the values for the dimensions shown in the illustration. Figure 34. QFN-38 Land Pattern Drawing Si3210/Si3211 Rev. 1.5 133 ...
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Si3210/Si3211 Table 49. QFN-38 PCB Land Pattern Dimensions Dimension C1 Pad column spacing C2 Pad row spacing E X1 Pin pad width X2 Thermal pad width Y1 Pin pad width Y2 Thermal pad length Notes: General 1. All dimensions shown ...
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TSSOP 8.2.1. Package Outline: 38-Pin TSSOP Figure 35 illustrates the package details for the Si321x. Table 50 lists the values for the dimensions shown in the illustration. Figure 35. 38-Pin Thin Shrink Small Outline Package (TSSOP) Table 50. ...
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Si3210/Si3211 8.2.2. PCB Land Pattern: 38-Pin TSSOP Figure 36 illustrates the recommended land pattern for the Si3210/11 TSSOP-38 package. Table 51 lists the values for the dimensions shown in the illustration. Figure 36. TSSOP-38 PCB Land Pattern Drawing Table 51. ...
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ESOIC 8.3.1. Package Outline: 16-Pin ESOIC Figure 37 illustrates the package details for the Si3201. Table 52 lists the values for the dimensions shown in the illustration. Figure 37. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package ...
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Si3210/Si3211 8.3.2. PCB Land Pattern: 16-Pin ESOIC Figure 38 illustrates the recommended land pattern for the Si3201 SOIC-16 package. Table 53 lists the values for the dimensions shown in the illustration. Figure 38. SOIC-16 PCB Land Pattern Drawing Table 53. ...
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Product Identification 9.1. Ordering Part Number The ordering part number indicates the device number, device variant (optional), device revision level, package type, temperature range, and packing format, e.g., tape-and-reel, and identifies Silicon Laboratories as the manufacturer. It will be ...
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Si3210/Si3211 10. Package Marking (Top Mark) 10.1. QFN Package Table 54. Explanation of QFN Top Mark Line 1 Marking: Silicon Labs prefix Device number Device variant (optional) Separator Package/temperature range Line 2 Marking: YY=Year WW=Work Week TTTTTT=Mfg Code Line ...
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TSSOP Package Figure 40. TSSOP Top Mark Diagram Table 55. Explanation of TSSOP Top Mark Line 1 Marking: Silicon Labs prefix Device number Device variant (optional) Separator Package/temperature range Line 2 Marking: YY=Year WW=Work Week RFAIXX=Mfg Code Line 3 ...
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Si3210/Si3211 10.3. SOIC (Si3201) Package Table 56. Explanation of SOIC Top Mark Silicon Labs prefix Device number Line 1 Marking: Separator Package/temperature range Circle=0.5 mm Diameter Center-Justified Circle=1.3 mm Diameter Lower Left-Justified Line 2 Marking: YY=Year WW=Work Week TTTTTT 142 ...
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... Figure 12, “Si3211 Typical Application Circuit Using Si3201,” on page 21. Added additional decoupling components to VDDA1, VDDA2, and VDDD. Figure 13, “Si3210/Si3210M Typical Application Circuit Using Discrete Components,” on page 23. Added additional decoupling components to VDDA1, VDDA2, and VDDD. Added optional components to STIPE, SRINGE, and ...
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Si3210/Si3211 Updated Table 16. Changed current rating 150 mA. Corrected missing reference to R5. Added new row for R26 and changed the value to 10 k. Added title for AN45 to description of ...
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N : OTES Si3210/Si3211 Rev. 1.5 145 ...
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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...