HBLXT9785HC.C2 Intel, HBLXT9785HC.C2 Datasheet - Page 199
HBLXT9785HC.C2
Manufacturer Part Number
HBLXT9785HC.C2
Description
Manufacturer
Intel
Datasheet
1.HBLXT9785HC.C2.pdf
(221 pages)
Specifications of HBLXT9785HC.C2
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LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 93
Cortina Systems
Port Configuration Register (Address 16, Hex 10)
®
1. R/W = Read/Write
2. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as
3. The default value of Register bit 16.0 is determined by the G_FX/TP_L pin.
4. The default value of Register bit 16.5 is determined by the PREASEL pin. The BGA15 package does not
5. The BGA15 package does not support fiber. Default for the BGA15 package is 0.
6. NA means the bits do not have a default value and may initially contain any value.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Bit
15
14
13
12
10
11
9
8
7
6
5
4
3
2
the pin(s) are latched at startup or hardware reset.
If G_FX/TP_L is tied Low, the default value of Register bit 16.0 = 0. If G_FX/TP_L is not tied Low, the
default value of Register bit 16.0 = 1. The BGA15 package does not have a G_FX/TP_L hardware
configuration pin.
have a PREASEL hardware configuration pin and has a default of 0.
Name
Reserved
Link Disable
Transmit Disable
Bypass Scramble
(100BASE-TX)
Reserved
Jabber
(10BASE-T)
Reserved
TP Loopback
(10BASE-T)
Reserved
Reserved
Preamble Enable
Reserved
Reserved
Far End Fault
Transmission
Enable
Invalid for
BGA15
Description
Write as 0, ignore on Read
0 = Normal operation
1 = Force link pass (sets appropriate registers and LEDs
Note: Setting this bit in 100 Mbps mode by-passes the
descrambler lock requirement to establish link and forces
the link to the link-good state. Setting this bit produces
unreliable results if the descrambler is not locked,
0 = Normal operation
1 = Disable twisted-pair transmitter
0 = Normal operation
1 = Bypass scrambler and descrambler
Write as 0, ignore on Read
0 = Normal operation
1 = Jabber function is enabled; however, jabber status
Write as 0, ignore on Read.
0 = Normal operation
1 = Disable twisted-pair loopback during half-duplex
Note: Valid function in SMII and S-SMII modes only.
Write as 1, ignore on Read
Write as 0, ignore on Read
10 Mbps
100
Mbps
Write as 0, ignore on Read
Write as 0, ignore on Read
0 = Disable Far End Fault transmission
1 = Enable Far End Fault transmission
Write as '0', ignore on Read (BGA15).
to pass)
reporting to Register bit 1.1 is disabled
operation
0 = No preamble (default)
1 = Preamble enabled
Note:
No effect
Default for BGA15 package is 0.
7.0 Register Definitions
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
Page 199
LSHR
Default
N/A
0
0
0
0
0
0
0
1
1
0
0
0
1
2,4
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