HBLXT9785HC.C2 Intel, HBLXT9785HC.C2 Datasheet - Page 106
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HBLXT9785HC.C2
Manufacturer Part Number
HBLXT9785HC.C2
Description
Manufacturer
Intel
Datasheet
1.HBLXT9785HC.C2.pdf
(221 pages)
Specifications of HBLXT9785HC.C2
Lead Free Status / RoHS Status
Not Compliant
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LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
3.6
3.6.1
3.6.2
Table 39
Cortina Systems
BGA15 Signal Descriptions
Signal Name Conventions
Signal names may contain either a port designation or a serial designation, or a
combination of the two designations. Signal naming conventions are as follows:
Signal Descriptions – SMII and SS-SMII Configurations
Table 39
BGA15 Signal Descriptions (Sheet 1 of 7)
®
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =
2. Switched to TPIP/N Inputs when MDIX is not active (twisted-pair, non-crossover MDI mode).
3. Switched to TPOP/N Outputs when MDIX is not active (twisted-pair, non-crossover MDI mode).
• Port Number Only. Individual signals that apply to a particular port are designated by
• Serial Number Only. A set of signals which are not tied to any specific port are
• Port and Serial Number. In cases where each port is assigned a set of multiple
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
the Signal Mnemonic, immediately followed by the Port Designation. For example,
Transmit Enable signals would be identified as TxEN0, TxEN1, and TxEN2.
designated by the Signal Mnemonic, followed by an underscore and a serial
designation. For example, a set of three Global Configuration signals would be
identified as CFG_1, CFG_2, and CFG_3.
signals, each signal is designated in the following order: Signal Mnemonic, Port
Designation, an underscore, and the serial designation. For example, a set of three
Port Configuration signals would be identified as RxData0_0 and RxData0_1,
RxData1_0 and RxData1_1, and RxData2_0 and RxData2_1.
Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-
Down.
REFCLK1
REFCLK0
TxData0
TxData1
TxData2
TxData3
TxData4
TxData5
TxData6
TxData7
Symbol
SYNC
provides the BGA15 signal descriptions.
Designation
BGA15 Ball
N4,
N2,
K3,
G3,
E2,
D3,
J1,
A5
C3
K1
L4
SMII/SS-SMII Common Signal Descriptions
SMII Specific Signal Descriptions
Type
I, ID
I, ID
I
Signal Description
Transmit Data - Ports 0-7.
These serial input streams provide data to be transmitted to
the network. The LXT9785/LXT9785E clocks the data in
synchronously to REFCLK.
Reference Clock.
The LXT9785/LXT9785E always requires a 125 MHz
reference clock input. Refer to
Requirements, on page 122
requirements.
SMII Synchronization.
The MAC must generate a SYNC pulse every 10 REFCLK
cycles to synchronize the SMII.
3.6 BGA15 Signal Descriptions
for detailed clock
Section 4.4.2, Clock/SYNC
Page 106
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