HBLXT9785HE.D0 Intel, HBLXT9785HE.D0 Datasheet - Page 187
HBLXT9785HE.D0
Manufacturer Part Number
HBLXT9785HE.D0
Description
Manufacturer
Intel
Datasheet
1.HBLXT9785HE.D0.pdf
(221 pages)
Specifications of HBLXT9785HE.D0
Lead Free Status / RoHS Status
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Part Number:
HBLXT9785HE.D0
Manufacturer:
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LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Figure 56
Table 78
Figure 57
Cortina Systems
RMII - 10BASE-T Transmit Timing
RMII - 10BASE-T Transmit Timing Parameters
Auto-Negotiation and Fast Link Pulse Timing
®
TxData<1:0>/TxEN setup to REFCLK rising
edge
TxData<1:0>/TxEN hold from REFCLK rising
edge
TxEN sampled to TPFO out (Tx latency)
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
Note:
TPFOP
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
testing.
100BASE-TX or 100BASE-FX).
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
TxData(1:0)
REFCLK
TPFO
TxEN
Parameter
Clock Pulse
t1
t
1
t2
t
3
Data Pulse
Sym
t1
t2
t3
t1
t3
t
1
Min
t
4
2
–
2
Typ1
8.5
–
–
Max
Clock Pulse
14
–
–
6.0 Test Specifications
Units
BT
ns
ns
2
t
2
Conditions
Page 187
Test
–
–
–
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