HBLXT9785HE.D0 Intel, HBLXT9785HE.D0 Datasheet - Page 15
![no-image](/images/manufacturer_photos/0/3/336/intel_sml.jpg)
HBLXT9785HE.D0
Manufacturer Part Number
HBLXT9785HE.D0
Description
Manufacturer
Intel
Datasheet
1.HBLXT9785HE.D0.pdf
(221 pages)
Specifications of HBLXT9785HE.D0
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HBLXT9785HE.D0
Manufacturer:
INTEL
Quantity:
20 000
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LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Cortina Systems
Page
116
119
120
130
131
136
145
146
148
148
149
149
150
151
152
153
158
166
170
171
173
174
175
175
176
36
42
42
43
1
Description
Changed "pseudo-ECL (PECL)" to "Low Voltage Positive Emitter Coupled Logic (LVPECL)" in the second
paragraph, front page.
Modified Table 5 “Cortina Systems
sentence to RXER0 through RXER7 signal description.
Modified Table 10 “Cortina Systems
Modified Table 11 “Cortina Systems
Modified Table 13 “Cortina Systems
note to PREASEL signal description.
Modified Section 4.1, “Introduction”. Changed "Pseudo-ECL (PECL)" to "Low Voltage PECL (LVPECL)" in the first
paragraph, second sentence.
Replace text under Section 4.2.1.3, “Fiber Interface”.
Modified Section 4.3.2, “Internal Loopback”.
Modified last sentence under Section 4.6.1.4, “Link Criteria”.
Modified text under Section 4.6.1.5, “Parallel Detection”. Added second paragraph.
Modified text under Section 4.7.4.3, “Receive Error”.
Changed "PECL" to "LVPECL in third paragraph, first sentence under Section 4.9.1, “100BASE-X Network
Operations”.
Modified Figure 28 “Cortina Systems
Modified Section 4.9.3.3, “Carrier Sense/Data Valid (RMII)”. Changed “asynchronously to “synchronously.”
Modified text under Section 4.9.3.4, “Carrier Sense (SMII)”. Revised last sentence in first paragraph.
Modified paragraph under Section 4.9.3.6.3, “Polarity Correction”.
Replaced text under Section 4.9.3.7, “Fiber PMD Sublayer”.
Modified Section 4.10.1, “Preamble Handling”. Added text to last paragraph.
Modified first sentence under Section 4.10.4, “Jabber”.
Modified first paragraph of Section 4.11, “DTE Discovery Process”.
Modified Item 1 of Section 4.11.2, “Interaction between Processor, MAC, and PHY”.
Modified Section 4.12.3, “Out-of-Band Signaling”. Added sentence to end of first paragraph.
Replaced text under Section 5.2.5, “The Fiber Interface”.
Replaced Figure 36 “Recommended Cortina Systems
Circuitry”.
Replaced Figure 37 “Recommended Cortina Systems
Circuitry”.
Modified Table 52 “Cortina Systems
Modified Table 53 “Cortina Systems
V +/- 5%)”.
Modified Table 54 “Cortina Systems
V +/- 5%)”.
Added Table 55 “Cortina Systems
Modified Table 58 “Cortina Systems
®
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Revision Number: 006 (INTERNAL RELEASE)
Revision Date: June 10, 2003
®
®
®
LXT9785/LXT9785E Digital I/O DC Electrical Characteristics – SD Pins”.
®
®
®
®
®
®
LXT9785/LXT9785E RMII Signal Descriptions – PQFP”. Added last
®
LXT9785/LXT9785E Network Interface Signal Descriptions – PQFP”,
LXT9785/LXT9785E Signal Detect – PQFP”.
LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP”. Added
LXT9785/LXT9785E Operating Conditions”.
LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 2.5
LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 3.3
LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics”.
LXT9785/LXT9785E Protocol Sublayers”.
®
®
LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface
LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface
Revision History
Page 15
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