L80223 LSI, L80223 Datasheet - Page 30

• Manufacturer Part Number: L80223
• Manufacturer: LSI

Specifications of L80223

• Lead Free Status / RoHS Status: Not Compliant

2.3.3 Encoder
2-12
MII (10 Mbits/s) – MII 10 Mbits/s operation is identical to 100 Mbits/s
operation except
MII Disable – To disable the MII inputs and outputs, set the MII_DIS bit
in the MI serial port Control register. When the MII is disabled, the MII
inputs are ignored, and the MII and TP outputs are placed in a high-
impedance state.
If the MI address lines, MDA[3:0]n, are pulled HIGH during reset or
powerup, the L80227 powers up and resets with the MII disabled.
Otherwise, the L80227 powers up and resets with the MII enabled.
This section describes the 4B5B encoder, which is used in 100 Mbits/s
operation. It also describes the Manchester Encoder, used in 10BASE-T
operation.
Functional Description
TX_CLK and RX_CLK clock frequency is reduced to 2.5 MHz
TX_ER is ignored
RX_ER is disabled and always held LOW
Receive operation is modified as follows:
On the receive side, when the squelch circuit determines that invalid
data is present on the TP inputs, the receiver is idle. During idle,
RX_CLK follows TX_CLK, RXD[3:0] is held LOW, and CRS and
RX_DV are deasserted. When a start of packet is detected on the
TP receive inputs, CRS is asserted and the clock recovery process
starts on the incoming TP input data. After the receive clock is
recovered from the data, the RX_CLK is switched over to the
recovered clock and the data valid signal RX_DV is asserted on a
falling edge of RX_CLK. Once RX_DV is asserted, valid data is
clocked out on RXD[3:0] on the falling edge of RX_CLK. The
RXD[3:0] data has the same packet structure as the TXD[3:0] data
and is formatted on RXD[3:0] as specified in IEEE 802.3 and shown
in
are deasserted. CRS and RX_DV also stay deasserted as long as
the device is in the Link Fail State.
Figure
2.3. When the end of packet is detected, CRS and RX_DV
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