FWLXT9785BC.A4 Intel, FWLXT9785BC.A4 Datasheet - Page 188

• Manufacturer Part Number: FWLXT9785BC.A4
• Manufacturer: Intel

Specifications of FWLXT9785BC.A4

• Lead Free Status / RoHS Status: Not Compliant

188
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 49. SS-SMII - 10BASE-T Receive Timing
Table 70. SS-SMII - 10BASE-T Receive Timing Parameters
REFCLK rising edge to RxCLK rising
edge
RxData/RxSYNC output delay from
RxCLK rising edge
RxData/RxSYNC Rise/Fall time
Receive Start-of-Frame to CRS asserted
Receive Start-of-Idle to CRS de-asserted
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. Assumes each SMII segment is sampled for CRS.
3. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
testing.
100BASE-TX or 100BASE-FX).
default configuration of 00 (32 bits of initial fill).
RxSYNC
REFCLK
RxData
RxCLK
Parameter
TPFI
t
4
Sym
t
1
t1
t2
t3
t4
t5
t
2
Min
1.5
–
–
–
–
Typ
1.5
10
18
–
1
1
Max
t
11
21
3
–
5
–
Units
BT
BT
ns
ns
ns
3
3
t
5
Minimum C
Maximum C
Synchronous sampling of
SMII
Synchronous sampling of
SMII
Revision Date: 30-May-2006
Document Number: 249241
Test Conditions
2
2
Revision Number: 010
L
L
–
–
= 5pF
Datasheet
= 40pF