FWLXT9785BC.A4 Intel, FWLXT9785BC.A4 Datasheet - Page 129

• Manufacturer Part Number: FWLXT9785BC.A4
• Manufacturer: Intel

Specifications of FWLXT9785BC.A4

• Lead Free Status / RoHS Status: Not Compliant

4.6.1.2
4.6.1.3
4.6.1.4
4.6.1.5
Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Manual Next Page Exchange
Additional information, exceeding that required by base page exchange, is also sent via “Next
Pages.” The LXT9785/LXT9785E fully supports the IEEE 802.3 method of negotiation via Next
Page exchange. The Next Page exchange uses Register 7 to send information and Register 8 to
receive it. Next Page exchange occurs only if both ends of the link partners advertise their ability to
exchange Next Pages. A special mode has been added to make manual next page exchange easier
for software. When Register 6 “page” is received, it stays set until read. This bit is cleared when a
new negotiation occurs, preventing the user from reading an old value in Register 6 and assuming
there is valid information in Registers 5 and 8. The page received bit is cleared upon reading the
“Auto-Negotiation Expansion Register (Address 6)” on page
Controlling Auto-Negotiation
The following steps are recommended when auto-negotiation is controlled by software:
Link Criteria
In 100 Mbps mode, link is established when the descrambler becomes locked and remains locked
for approximately 50 ms. Link remains up unless the descrambler receives less than 16 consecutive
idle symbols in any 2 ms period. This provides a robust operation, filtering out any small noise hits
that may disrupt the link.
MLT-3 idle waveforms, for short periods, meet all the criteria for 10BASE-T start delimiters. A
working 10BASE-T receive may temporarily indicate link to 100BASE-TX waveforms. However,
the PHY will not bring up a permanent 10 Mbps link.
According to the IEEE standard 10 Mbps link state machine, the last condition that must be met
before 10 Mbps link can come up is a period of transmit and receive idle time. TXEN and RXDV
are inactive at the same time. This ensures that link is not brought up in the middle of transmitting
or receiving a packet. To ensure link establishment, Intel recommends no packet transmission into
the MII interface until link is established.
The IEEE Standard references this requirement in Section 14.2.3 State Diagrams, Figure 14-6-Link
Integrity Test Function State Diagram and in Section 28.3.4 State Diagrams, Figure 28-17-NLP
Receive Link Integrity Test State Diagram. These diagrams illustrate that while the PHY is in the
Link Test Fail Extend state, the last state before Link Pass state) Packet receive activity (RD) and
Transmit Activity (DO) must be idle (RD = idle * D0 = idle) for link to establish.
Parallel Detection
In parallel with auto-negotiation, the LXT9785/LXT9785E also monitors for 10 Mbps Normal
Link Pulses (NLP) or 100 Mbps Idle symbols. If either symbol is detected, the device
automatically reverts to the corresponding operating speed in half-duplex mode. Parallel detection
allows the LXT9785/LXT9785E to communicate with devices that do not support auto-
negotiation.
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After power-up, power-down, or reset, the power-down recovery time, as specified in
Table 80, “Power-Up Timing Parameters” on page
Set the auto-negotiation advertisement register bits in Register 4 as desired.
Enable auto-negotiation (set MDIO Register bit 0.12 = 1).
Enable or restart auto-negotiation as soon as possible after writing to Register 4 to ensure
proper operation.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
198, must be exhausted before proceeding.
206.
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