DJLXT971ALE.A4 S E001 Cortina Systems Inc, DJLXT971ALE.A4 S E001 Datasheet - Page 40

• Manufacturer Part Number: DJLXT971ALE.A4 S E001
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT971ALE.A4 S E001

• Lead Free Status / RoHS Status: Not Compliant

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
.
Table 14
5.6.5
5.6.6
5.6.7
Cortina Systems
100 Mbps
10 Mbps
1. Test Loopback is enabled when register bit 0.14 = 1.
2. For descriptions of Test Loopback and Operational Loopback, see
Carrier Sense, Loopback, and Collision Conditions
Error Signals
When the LXT971A PHY is in 100 Mbps mode and receives an invalid symbol from the
network, it asserts RX_ER and drives “0101” on the RXD pins.
When the MAC asserts TX_ER, the LXT971A PHY drives “H” symbols out on the TPFOP/
N pins.
Collision
The LXT971A PHY asserts its collision signal asynchronously to any clock whenever the
line state is half-duplex and the transmitter and receiver are active at the same time.
Table 14
collision signals.
Loopback
The LXT971A PHY provides the following loopback functions:
Figure 13
loopback path is not shown.) For more information on loopback functions, see
Carrier Sense, Loopback, and Collision Conditions, on page
®
Speed
•
•
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Section 5.6.7.1, Operational Loopback
Section 5.6.7.2, Internal Digital Loopback (Test Loopback)
summarizes the conditions for assertion of carrier sense, data loopback, and
Full-Duplex
Half-Duplex
Full-Duplex
Half-Duplex,
register bit 16.8 = 0
Half-Duplex,
register bit 16.8 = 1
Duplex Condition
shows LXT971A PHY operational and test loopback paths. (An internal digital
Receive Only
Transmit or Receive
Receive Only
Transmit or Receive
Transmit or Receive
Carrier Sense
Loop-
back
Test
Yes
Yes
Yes
No
No
1, 2
Section 5.6.7, Loopback , on page
Operational
back
Loop-
40.)
Yes
No
No
No
No
1, 2
None
Transmit and Receive
None
Transmit and Receive
Transmit and Receive
5.6 MII Operation
Collision
Table 14,
Page 40
40.