L-FW802B-DB LSI, L-FW802B-DB Datasheet - Page 9

• Manufacturer Part Number: L-FW802B-DB
• Manufacturer: LSI

Specifications of L-FW802B-DB

• Lead Free Status / RoHS Status: Compliant

Data Sheet, Rev. 3
May 2004
Signal Information
Table 1. Signal Descriptions (continued)
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.
Agere Systems Inc.
Pin
61
28
29
63
36
35
41
40
34
33
39
38
SYSCLK
/RESET
Signal*
TPB0+
TPA0+
TPA0−
TPA1+
TPA1−
TPB0−
TPB1+
TPB1−
SM
SE
(continued)
Analog I/O Port0, Port Cable Pair A. TPA0± is the port A connection to the twisted-
Analog I/O Port1, Port Cable Pair A. TPA1± is the port A connection to the twisted-
Analog I/O Port0, Port Cable Pair B. TPB0± is the port B connection to the twisted-
Analog I/O Port1, Port Cable Pair B. TPB1± is the port B connection to the twisted-
Type
O
I
I
I
Reset (Active-Low). When /RESET is asserted low (active), a 1394 bus
reset condition is set on the active cable ports and the FW802B is reset to
the reset start state. To guarantee that the PHY will reset, this pin must be
held low for at least 2 ms. An internal pull-up resistor connected to V
provided so that only an external delay capacitor (0.1 µF) and resistor
(510 kΩ), in parallel, are required to connect this pin to ground. This
circuitry will ensure that the capacitor will be discharged when PHY power
is removed. This input is a standard logic buffer and can also be driven by
an open-drain logic output buffer. Do not leave this pin unconnected.
Test Mode Control. SE is used during Agere’s manufacturing test and
should be tied to V
Test Mode Control. SM is used during Agere’s manufacturing test and
should be tied to V
System Clock. SYSCLK provides a 49.152 MHz clock signal, which is
synchronized with the data transfers to the LLC.
pair cable. Board traces from each pair of positive and negative differen-
tial signal pins should be kept as short as possible and matched to the
external load resistors and to the cable connector. When the FW802B’s
1394 port pins are not wired to a connector, the unused port pins may be left
unconnected. Internal connect-detect circuitry will keep the port in a discon-
nected state.
pair cable. Board traces from each pair of positive and negative differen-
tial signal pins should be kept as short as possible and matched to the
external load resistors and to the cable connector. When the FW802B’s
1394 port pins are not wired to a connector, the unused port pins may be
left unconnected. Internal connect-detect circuitry will keep the port in a
disconnected state.
pair cable. Board traces from each pair of positive and negative differen-
tial signal pins should be kept as short as possible and matched to the
external load resistors and to the cable connector. When the FW802B’s
1394 port pins are not wired to a connector, the unused port pins may be
left unconnected. Internal connect-detect circuitry will keep the port in a
disconnected state.
pair cable. Board traces from each pair of positive and negative differen-
tial signal pins should be kept as short as possible and matched to the
external load resistors and to the cable connector. When the FW802B’s
1394 port pins are not wired to a connector, the unused port pins may be
left unconnected. Internal connect-detect circuitry will keep the port in a
disconnected state.
SS
SS
FW802B Low-Power PHY IEEE 1394A-2000
for normal operation.
for normal operation.
Two-Cable Transceiver/Arbiter Device
Name/Description
DD
is
9