L-FW802B-DB LSI, L-FW802B-DB Datasheet - Page 7

• Manufacturer Part Number: L-FW802B-DB
• Manufacturer: LSI

Specifications of L-FW802B-DB

• Lead Free Status / RoHS Status: Compliant

Data Sheet, Rev. 3
May 2004
Signal Information
Table 1. Signal Descriptions
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.
Agere Systems Inc.
9, 10, 11,
5, 6, 8,
12, 13
Pin
18
15
24
3
4
C/LKON
Signal*
D[0:7]
CTL0
CTL1
CNA
CPS
(continued)
Type
I/O
I/O
I/O
O
I
Note: When this pin is grounded, the Pwr_fail bit in PHY register 0101
Note: If an interrupt condition exists which would otherwise cause the
Bus Manager Capable Input and Link-On Output. On hardware reset
(/RESET), this pin is used to set the default value of the contender status
indicated during self-ID. The bit value programming is done by tying the
signal through a 10 kΩ resistor to V
GND (low, not bus manager capable). Using either the pull-up or pull-
down resistor allows the link-on output to override the input value when
necessary.
After hardware reset, this pin is set as an output. If the LPS is inactive,
C/LKON indicates one of the following events by asserting a 6.114 MHz
signal.
1. FW802B receives a link-on packet addressed to this node.
2. Port_event register bit is 1.
3. Any of the Timeout, Pwr_fail, or Loop register bits are 1 and the
4. Once activated, the C/LKON output will continue active until the LPS
Cable-Not-Active Output. CNA is asserted high when none of the PHY
ports are receiving an incoming bias voltage. This circuit remains active
during the powerdown mode.
Cable Power Status. CPS is normally connected to the cable power
through a 400 kΩ resistor. This circuit drives an internal comparator that
detects the presence of cable power. This information is maintained in one
internal register and is available to the LLC by way of a register read (see
Table 8, address register 0000
or source 1394 power (VP), this pin can be tied to ground.
Control I/O. The CTLn signals are bidirectional communications control
signals between the PHY and the LLC. These signals control the passage
of information between the two devices. Bus-keeper circuitry is built into
these terminals.
Data I/O. The Dn signals are bidirectional and pass data between the
PHY and the LLC. Bus-keeper circuitry is built into these terminals.
1394 bus reset occurs, if the C/LKON is active due solely to the recep-
Watchdog register bit is also 1.
becomes active. The PHY also deasserts the C/LKON output when a
tion of a link-on packet.
be set.
C/LKON output to be activated if the LPS were inactive, the
C/LKON output will be activated when the LPS subsequently
becomes inactive.
FW802B Low-Power PHY IEEE 1394A-2000
Two-Cable Transceiver/Arbiter Device
Name/Description
2
, bit 7/PS). In applications that do not sink
DD
(high, bus manager capable) or to
2
will
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