LULXT9785MBC.D0-865133 Cortina Systems Inc, LULXT9785MBC.D0-865133 Datasheet - Page 116
LULXT9785MBC.D0-865133
Manufacturer Part Number
LULXT9785MBC.D0-865133
Description
Manufacturer
Cortina Systems Inc
Datasheet
1.LULXT9785MBC.D0-865133.pdf
(221 pages)
Specifications of LULXT9785MBC.D0-865133
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LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
4.2.1.2
Table 40
Note:
4.2.1.3
Note:
4.3
Note:
Cortina Systems
MDI Crossover (MDIX)
The LXT9785/LXT9785E crossover function, which is compliant to the IEEE 802.3, clause
23 standard, connects the transmit output of the device to the far-end receiver in a link
segment. This function can be disabled via Register bits 27.9:8 or by using the hardware
configuration pins.
MDIX Selection
The BGA15 package does not support MDIX hardware configuration. Software must be
used to control the function after power-up.
Fiber Interface
The LXT9785/LXT9785E fiber ports are designed to interface with common industry-
standard 3.3 V and 5 V fiber transceivers. Each of the 8 ports incorporates a Low-Voltage
PECL interface that complies with the ANSI X3.166 standard for seamless integration.
The BGA15 package does not support the fiber interface.
Fiber mode is selected through Register bit 16.0 by the following two methods:
The fiber interface is capable of full-duplex or half-duplex operation. In half duplex,
operation collisions must be managed by external Layer 2 logic (MAC). Auto negotiation is
not supported for fiber mode.
Media Independent Interface (MII) Interfaces
The LXT9785/LXT9785E supports Reduced MII or Serial MII, but not concurrently. The
interface mode selection pins configures the device for either RMII or SMII/SS-SMII on all
eight ports. Refer to
The BGA15 package does not support the RMII interface.
®
1. Configure Register bit 16.0 = 1 on a global basis (all 8 ports) by driving the Hardware
2. Configure Register bit 16.0 = 1 on a per-port basis through the MDIO interface.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
AMDIX_EN
Control pin G_FX/TP_L to a logic High value on power-up and/or reset.
0
0
1
Table 41
MDIX
X
0
1
for the mode select settings.
Auto MDI/MDIX
MDIX Mode
MDIX forced
MDI forced
Interface (MII) Interfaces
4.3 Media Independent
Page 116
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