EGLXT973QCA3V-873168 Cortina Systems Inc, EGLXT973QCA3V-873168 Datasheet - Page 90
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EGLXT973QCA3V-873168
Manufacturer Part Number
EGLXT973QCA3V-873168
Description
Manufacturer
Cortina Systems Inc
Datasheet
1.EGLXT973QCA3V-873168.pdf
(97 pages)
Specifications of EGLXT973QCA3V-873168
Lead Free Status / RoHS Status
Compliant
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LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
Table 49
Figure 41
Table 50
Cortina Systems
MDIO Timing Parameters (Sheet 2 of 2)
Power-Up Timing
Power-Up Timing Parameters
®
MDIO hold after MDC
MDC to MDIO output delay
MDC Clock Speed
1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to
2. When operated at 2.5 MHz.
Voltage threshold
Power-up delay
1. Typical values are at 25
2. Power-up delay is specified as a maximum value because it refers to the guaranteed performance of the
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
MDIO,etc.
production testing.
testing.
PHY. The PHY comes out of reset after a delay of no more than 300 μ S. System designers should
consider this as a minimum value. After threshold
300 μ S before accessing the MDIO port.
VCC
Parameter
Parameter
2
o
C and are for design aid only; not guaranteed and not subject to producing
Sym
Sym
v1
t2
t3
t4
t1
Min
Min
2.9
10
10
–
–
v
V
1 is reached, the MAC should delay no less than
Typ
Typ
–
–
–
–
–
1
1
Max
300
Max
300
20
–
–
2
t
Units
Units
MHz
ns
ns
μ s
15.0 Timing Diagrams
V
When sourced
by STA
When sourced
by PHY
Conditions
Conditions
Test
Test
–
–
–
Page 90
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