LAN8187-JT Standard Microsystems (SMSC), LAN8187-JT Datasheet - Page 54

• Manufacturer Part Number: LAN8187-JT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN8187-JT

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Compliant

Revision 1.6 (02-27-09)
5.4.9
5.4.9.1
5.4.9.2
MODE[2:0]
Ethernet
000
001
010
011
10/100
MAC
transmit signals an the output of the transformer back to the receiver inputs, and this loopback will
work at both 10 and 100.
Configuration Signals
The PHY has 11 configuration signals whose inputs should be driven continuously, either by external
logic or external pull-up/pull-down resistors.
Physical Address Bus - PHYAD[4:0]
The PHYAD[4:0] signals are driven high or low to give each PHY a unique address. This address is
latched into an internal register at end of hardware reset. In a multi-PHY application (such as a
repeater), the controller is able to manage each PHY via the unique address. Each PHY checks each
management data frame for a matching address in the relevant bits. When a match is recognized, the
PHY responds to that particular frame. The PHY address is also used to seed the scrambler. In a multi-
PHY application, this ensures that the scramblers are out of synchronization and disperses the
electromagnetic radiation across the frequency spectrum.
Mode Bus – MODE[2:0]
The MODE[2:0] bus controls the configuration of the 10/100 digital block. When the nRST pin is de-
asserted, the register bit values are loaded according to the MODE[2:0] pins. The 10/100 digital block
is then configured by the register bit values. When a soft reset occurs (bit 0.15) as described in
Table
MODE[2:0] pins have no affect.
10Base-T Half Duplex. Auto-negotiation disabled.
10Base-T Full Duplex. Auto-negotiation disabled.
100Base-TX Half Duplex. Auto-negotiation
disabled.
CRS is active during Transmit & Receive.
100Base-TX Full Duplex. Auto-negotiation disabled.
CRS is active during Receive.
TXD
5.30, the configuration of the 10/100 digital block is controlled by the register bit values, and the
RXD
Digital
Ethernet Transceiver
Figure 5.4 Connector Loopback Block Diagram
MODE DEFINITIONS
SMSC
Table 5.48 MODE[2:0] Bus
±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR
Analog
DATASHEET
54
TX
RX
XFMR
DEFAULT REGISTER BIT VALUES
REGISTER 0
[13,12,10,8]
0000
0001
1000
1001
RJ45 Loopback Cable.
Created by connecting pin 1 to pin 3
and connecting pin 2 to pin 6.
SMSC LAN8187/LAN8187i
1
2
3
4
5
6
7
8
REGISTER 4
[8,7,6,5]
N/A
N/A
N/A
N/A
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