CPC7594MB IXYS, CPC7594MB Datasheet - Page 15

• Manufacturer Part Number: CPC7594MB
• Manufacturer: IXYS

Specifications of CPC7594MB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

1. Pull T
2. Keep T
3. During the T
4. Release T
2.4 Data Latch
The CPC7594 has an integrated transparent data
latch. The latch enable operation is controlled by TTL
logic input levels at the LATCH pin. Data input to the
latch is via the input pins IN
the output of the data latch are internal nodes used for
state control. When the LATCH enable control pin is at
a logic 0 the data latch is transparent and the input
control signals flow directly through the data latch to
the state control circuitry. A change in input will be
reflected by a change in the switch state.
Whenever the LATCH enable control pin is at logic 1,
the data latch is active and data is locked. Subsequent
changes to the input controls IN
will not result in a change to the control logic or affect
the existing switch state.
R01.1
Ringing
Before-
Break-
All-Off
State
Make
Talk
This opens the ringing return switch (SW3) and
prevents any other switches from closing.
the ringing cycle period to allow sufficient time for
a zero crossing current event to occur and for the
circuit to enter the break-before-make state.
IN
activate the break switches.
TEST
SD
IN
SD
inputs to the talk state (0, 0).
RINGING
to a logic low to end the ringing state.
1
1
0
0
low for at least one-half the duration of
SD
SD
, allowing the internal pull-up to
low period, set the IN
IN
TEST
0
0
0
0
2.3.5 Table 1: Alternate Break-Before-Make Ringing to Talk Transition Logic Sequence
RINGING
LATCH
RINGING
0
X
0
and IN
T
and IN
Z
Z
SD
0
RINGING
TEST
Hold this state for at least one-half of the
TEST
while
ringing cycle. SW4 waiting for zero
and
www.clare.com
Close Break Switches
current to turn off.
SW4 has opened
Timing
When using T
states are “0” which overrides the logic input pins and
forces an all off state and “Z” which allows normal
switch control via the logic input pins. This requires the
use of an open-collector or open-drain type buffer.
Forcing T
detecting a thermal shutdown condition and is
therefore not recommended.
The switches will remain in the state they were in
when the LATCH changes from logic 0 to logic 1 and
will not respond to changes in input as long as the
LATCH is at logic 1. However, neither the T
nor the T
the latch function. Since internal thermal shutdown
control and external “All-off” control is not affected by
the state of the LATCH enable input, T
state control.
2.5 T
The T
internal pull-up current source having a nominal value
of 16 µA biased from V
As an output, this pin indicates the status of the
thermal shutdown circuitry. Typically, during normal
operation, this pin will be pulled up to V
fault conditions that create excess thermal loading the
CPC7594 will enter thermal shutdown and a logic low
will be output.
-
SD
SD
Pin Description
SD
pin is a bi-directional I/O structure with an
SD
output control functions are affected by
to a logic high prevents the user from
SD
as an input, the two recommended
Switches
Break
Off
Off
Off
On
DD
.
Ringing
Return
Switch
(SW3)
On
Off
Off
Off
Ringing
Switch
(SW4)
SD
On
On
Off
Off
DD
will override
but under
CPC7594
SD
Switches
input
Test
Off
Off
Off
Off
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