CY7C955-NC Cypress Semiconductor Corp, CY7C955-NC Datasheet - Page 69

• Manufacturer Part Number: CY7C955-NC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C955-NC

• Lead Free Status / RoHS Status: Not Compliant

Functional Timing Diagram
Utopia Interface (Transmit Side) Functional Timing
Figure 8 shows, in a nutshell, all the functional timing require-
ments of the Transmit Side Utopia Interface. The Transmit Side
Utopia Interface consists of TDAT[7:0], TXPRTY, TSOC,
TWRENB, TCA, and TFCLK.
TDAT[7:0]
ATM cells are expected to be clocked into the Utopia FIFO
interface through TDAT[7:0] with the 1st header byte first fol-
lowed by the remaining 52 bytes of headers and payload. The
fifth header byte (HEC) is required but is being ignored and
replaced by the HCS octet generated by the Transmit ATM Cell
Processor.
TXPRTY
The TXPTYP (Reg 63, bit 7) and TXPRTYE (Reg 63H, bit 6)
can be set to make the Transmit Side Utopia Interface accept
odd, even, or no parity TXPRTY inputs.
TSOC
A HIGH TSOC input is expected along with the first header
byte of an ATM cell. If TSOC is absent, the Transmit ATM Cell
Processor will automatically generate a TSOC based on pre-
vious TSOC positions, no interrupt will be sent. However, if
TSOC is misplaced, the previously stored incomplete ATM cell
will be discarded and the transmit FIFO pointer will be set back
to the beginning of the same cell. A misplaced event will cause
TXPRTY
TFCLK
TSOC
TCA
TWNRENB
TDAT[7:0]
X
X
H1
H2
PRELIMINARY
H3
Figure 8. Transmit FIFO
P44
69
TSOCI (Reg 60H, bit 6) to go HIGH, and causes an interrupt
also if FIFOE (Reg 60H, bit 7) is enabled.
TWRENB
This transmit FIFO write enable bit (TWRENB) should be
pulled LOW whenever there is an ATM byte to send. It can be
deactivated at any time to pause the writing process—not nec-
essarily at cell boundaries.
TCA
The transmit cell available (TCA) is affected by TCAINV
(Reg 01H, bit 3) and TCALEVEL0 (Reg 63H, bit 94). TCAINV
determines the active polarity of the TCA signal, and
TCALEVEL0 controls the meaning of TCA going active. If
TCALEVEL0 = 0, TCA will be deasserted when the transmit
FIFO is 4 writes from full. If TCALEVEL0 = 1, TCA will be
deasserted when the FIFO is full and can accept no more
writes.
TFCLK
TFCLK has to be a clock of 33 MHz or less. Although it can be
stopped if necessary, it is not recommended because some
registers and pins synchronized by this clock will not be updat-
ed. If this clock is stopped, the line side interface will still be
able to transmit the cells already stored into the FIFO. After
that, idle cells will be transmitted.
P45
P46
TCA LEVEL 0 =1
P47
P48
X
X
CY7C955
H1