GD82559ER 824184 Intel, GD82559ER 824184 Datasheet - Page 29

• Manufacturer Part Number: GD82559ER 824184
• Manufacturer: Intel

Specifications of GD82559ER 824184

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

4.2.4
4.2.4.1
4.2.4.2
4.2.4.3
Datasheet
D0 Power State
D1 Power State
D2 Power State
Power States
The 82559ER’s power management register implements all four power states as defined in the
Power Management Network Device Class Reference Specification, Revision 1.0. The four states,
D0 through D3, vary from maximum power consumption at D0 to the minimum power
consumption at D3. PCI transactions are only allowed in the D0 state, except for host accesses to
the 82559ER’s PCI configuration registers. The D1 and D2 power management states enable
intermediate power savings while providing the system wake-up capabilities. In the D3
the 82559ER can provide wake-up capabilities only if auxiliary power is supplied. Wake-up
indications from the 82559ER are provided by the Power Management Event (PME#).
As defined in the Network Device Class Reference Specification, the device is fully functional in
the D0 power state. In this state, the 82559ER receives full power and should be providing full
functionality. In the 82559ER the D0 state is partitioned into two substates, D0 Uninitialized (D0u)
and D0 Active (D0a).
D0u is the 82559ER’s initial power state following a PCI RST#. While in the D0u state, the
82559ER has PCI slave functionality to support its initialization by the host and supports wake up
events. Initialization of the CSR, Memory, or I/O Base Address Registers in the PCI Configuration
space switches the 82559ER from the D0u state to the D0a state.
In the D0a state, the 82559ER provides its full functionality and consumes its nominal power. In
addition, the 82559ER supports wake on link status change (see
on page
clock frequency greater than 16 MHz) for proper operation. During idle time, the 82559ER
supports a PCI clock signal suspension using the Clockrun signal mechanism. The 82559ER
supports a dynamic standby mode. In this mode, the 82559ER is able to save almost as much
power as it does in the static power-down states. The transition to or from standby is done
dynamically by the 82559ER and is transparent to the software.
In order for a device to meet the D1 power state requirements, as specified in the Advanced
Configuration and Power Interface (ACPI) Specification, Revision 1.0, it must not allow bus
transmission or interrupts; however, bus reception is allowed. Therefore, device context may be
lost and the 82559ER does not initiate any PCI activity. In this state, the 82559ER responds only to
PCI accesses to its configuration space and system wake-up events.
The 82559ER retains link integrity and monitors the link for any wake-up events such as wake-up
packets or link status change. Following a wake-up event, the 82559ER asserts the PME# signal to
alert the PCI based system.
The ACPI D2 power state is similar in functionality to the D1 power state. If the bus is in the B2
state, the 82559ER will consume less current than it does in the D1 state. In addition to D1
functionality, the 82559ER can provide a lower power mode with wake-on-link status change
capability. The 82559ER may enter this mode if the link is down while the 82559ER is in the D2
state. In this state, the 82559ER monitors the link for a transition from an invalid link to a valid
link. The 82559ER will not attempt to keep the link alive by transmitting idle symbols or link
integrity pulses.
configuration bit in the Power Management Driver Register (PMDR).
27). While it is active, the 82559ER requires a nominal PCI clock signal (in other words, a
1
The sub-10 mA state due to an invalid link can be enabled or disabled by a
Networking Silicon — GD82559ER
Section 4.2.5, “Wake-up Events”
cold
state,
23