S19233PBIFB Applied Micro Circuits Corporation, S19233PBIFB Datasheet - Page 10

• Manufacturer Part Number: S19233PBIFB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19233PBIFB

• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

S19233 – 10 G Ethernet/Fibre Channel/SONET/SDH
Dual CDR
an LOS condition the PLL will lock to reference until
the LOS condition is de-asserted. LOS pin is not con-
figured as an open drain or open collector output.
The signal detect is an active high or active low LVTTL
single-ended input to be driven by the external optical
receiver module to indicate the presence of received
optical power. Active level (high or low) is programmed
by the SDPOL. When a loss-of-light condition occurs,
an active SD will cause the internal PLL to be locked
to the REFCLK input signal.
Receive Lock-to-Reference (LCKREFRXB) – I
Register
Active low. Lock-to-Reference (LCKREFRXB) input
register will force the PLL to lock to the local Refer-
ence Clock (REFCLK) when active. This bit should be
set to inactive which is default, for normal operation.
This input is only accessible through the I
register.
Receive Signal Detect Polarity (SDPOL) – I
ister
The signal detect polarity is an input bit that will set the
LOS_SD input as either active high or active low when
the LOS_SD bit is set inactive. Setting this pin low will
set the LOS_SD input as active low. Setting this bit
high will set the LOS_SD input as active high. This
input is only accessible through the I
Receive Squelch Serial Output (RX_SQ_EN) – I
Register
The Squelch Serial Output data enable (RX_SQ_EN),
when asserted high, will enable the squelch function in
the receiver.
10
2
C bus register.
2
C Reg-
2
C bus
2
C
2
C
TRANSMIT ELECTRICAL SIDE –
DESCRIPTION
Programmable Equalization
The transmit front end have programmable equaliza-
tion to compensate for 24 inches FR-4 applications.
Equalization is necessary to compensate for band-
width attenuation/distortions caused by the PWB.
Signal Conditioning Operation
On the Transmit side, the S19233 performs the signal
conditioning stage in the processing of a transmit
10 Gigabit Ethernet/10 G Fibre Channel/SONET STS-
192/ data stream. The rate will depend upon the REF-
CLK frequency used. A high-frequency bit clock is
generated from a 155 MHz (or equivalent FEC/
10 Gigabit Ethernet rate) frequency reference by using
a clock synthesizer consisting of an on-chip phase-
lock loop circuit with a divider, VCO and loop filter.
Clock Data Recovery – Transmit
The CDR shown in the block diagram in Figure 2, is a
monolithic PLL that generates the serial output clock
frequency locked to the input Reference Clock (REF-
CLKP/N) used by the receive side.
The REFCLKP/N input must be generated from a crys-
tal oscillator which has a frequency accuracy that
meets the value stated in Table 13 in order for the
Transmit Serial Data (TXDATOUTP/N) frequency to
have the accuracy required for operation in a SONET/
10 Gigabit Ethernet system. The REFCLK must also
meet the phase noise requirements shown in Figure 5
in order to meet the jitter generation specifications as
defined in GR-253-Core, Issue 3, September 2000.
Lower accuracy crystal oscillators may be used in
applications less demanding than the SONET/SDH.
The on-chip PLL consists of; a phase detector, which
compares the phase relationship between the VCO
output and the REFCLK input, a loop filter, which con-
verts the phase detector output into a smooth DC
voltage, and a VCO, whose frequency is varied by this
voltage.
The loop filter generates a VCO control voltage based
on the average DC level of the phase discriminator
output pulses. A single external clean-up capacitor is
utilized as part of the loop filter. The loop filter’s corner
frequency is optimized to minimize output phase jitter.
Revision 5.00 – March 16, 2007
AMCC Confidential and Proprietary
Data Sheet