WG82574IT S LBAB Intel, WG82574IT S LBAB Datasheet - Page 67
WG82574IT S LBAB
Manufacturer Part Number
WG82574IT S LBAB
Description
Manufacturer
Intel
Datasheet
1.WG82574IT_S_LBAB.pdf
(472 pages)
Specifications of WG82574IT S LBAB
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Compliant
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Initialization—82574 GbE Controller
Figure 13.
82574 Initialization - PHY and Manageability
Each PCIe register write takes ~20 PCIe clocks (31.25 MHz) per table entry <=>
640 ns per Dword. Each PHY register write takes those 20 clocks + 64 MDC cycles on
the MDIO interface (2.5 MHz) => 26.24 ms per Dword. Therefore, the total is 640 ns x
4 + 26.24 ms x 16 = 422 ms.
Each PCIe register write takes ~20 PCIe clocks (31.25 MHz) per table entry <=>
640 ns per Dword. Therefore, the bottleneck is the EEPROM at 40 ms per Dword. Each
PHY register write takes those 20 clocks + 64 MDC cycles on the MDIO interface (2.5
MHz) => 26.24 ms per Dword. Therefore, the bottleneck is the EEPROM at 40 ms per
Dword. The 16+4 entries take 20 Dwords x 40 ms = 0.8 s.
82574 set to default
Clear SW/HW NVM
semaphore
0
values
No need to load
Configuration
Extended
PHY was inactive up to
and/or wake up based
bits in NVM word 0x0F
Enable manageability
on NVM configuration
Based on MNG_Mode
Enable the PHY if
~0
11
Configuration from
Clear SW/HW NVM
needed
~0.42
Load Extended
now
Shadow RAM
D
semaphore
C
Flash
4
Configuration
Need to load
Extended
Configuration from
Clear SW/HW NVM
Load Extended
~0.8
semaphore
EEPROM
EEPROM
5
67
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