WG82574IT S LBAB Intel, WG82574IT S LBAB Datasheet - Page 254
WG82574IT S LBAB
Manufacturer Part Number
WG82574IT S LBAB
Description
Manufacturer
Intel
Datasheet
1.WG82574IT_S_LBAB.pdf
(472 pages)
Specifications of WG82574IT S LBAB
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Compliant
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9.1.2.15
9.1.2.16
9.1.2.17
9.1.2.18
9.1.3
Table 69.
254
Cap_Ptr (Offset 0x34)
The Capabilities Pointer field (Cap_Ptr) is an 8-bit field that provides an offset in the
device's PCI configuration space for the location of the first item in the capabilities
linked list. The 82574 sets this bit, and implements a capabilities list, to indicate that it
supports:
Its value, 0xC8, is the address of the first entry: PCI power management.
Interrupt Line (Offset 0x3C)
Read/write register programmed by software to indicate which of the system interrupt
request lines this device's interrupt pin is bound to. See the PCI definition for more
details.
Interrupt Pin (Offset 0x3D)
Read-only register. The LAN implements legacy interrupt on INTA.
Max_Lat/Min_Gnt (Offset 0x3E)
Not used. Hardwired to 0b.
PCI Power Management Registers
All fields are reset on full power up. All of the fields except PME_En and PME_Status are
reset on exit from D3cold state.
See the detailed description for registers loaded from the NVM at initialization time.
Initialization values of the configuration registers are marked in parenthesis.
Some fields in this section depend on the Power Management Ena bits in the NVM word
0x0A.
Table 69
fields are read only fields.
Power Management Register Block
Byte Offset
0xC8
0xCC
• PCI power management
• MSI
• MSI-X
• PCIe extended capabilities
0xC8-CF
0xD0-DF
0xA0-AB
0xE0-F3
Address
lists the organization of the PCI Power Management register block. Light-blue
Byte 3
Power Management Capabilities (PMC)
Data
PCI power management
MSI
MSI-X
PCIe Capabilities
Item
Byte 2
PMCSR_BSE Bridge
Support Extensions
0xD0
0xE0
0x00
0xA0
82574 GbE Controller—Programing Interface
Byte 1
Next Pointer
(0xD0)
Power Management Control / Status
Register (PMCSR)
Next Pointer
Byte 0
Capability ID
(0x01)
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