LAN91C96-MU Standard Microsystems (SMSC), LAN91C96-MU Datasheet - Page 32
![](/photos/31/30/313088/100pin_tqfp_sml.jpg)
LAN91C96-MU
Manufacturer Part Number
LAN91C96-MU
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN91C96-MU.pdf
(125 pages)
Specifications of LAN91C96-MU
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN91C96-MU
Manufacturer:
SMSC
Quantity:
1 430
Company:
Part Number:
LAN91C96-MU
Manufacturer:
Standard
Quantity:
2 701
Company:
Part Number:
LAN91C96-MU
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
LAN91C96-MU
Manufacturer:
SMSC
Quantity:
20 000
5.3
5.4
Revision 1.0 (10-24-08)
Interrupt Output
Ethernet Interrupt Source
Ethernet Interrupt Enable
Ethernet Interrupt Status Bit
RESET pin
ECOR
Register
SRESET bit
SOFT RST
Reset Logic
The pins and bits involved in the different reset mechanisms are:
RESET - Input Pin
SRESET - Soft Reset bit in ECOR, or the SRESET bit
SOFT RST - EPH Soft Reset bit in RCR
Power Down Logic States
Table 5.6, Table 5.7, Table 5.8, and Table 5.9 describe the power down states of the LAN91C96.
pins and bits involved in power down are:
1.
2.
3.
4.
FUNCTION
PWRDWN/TXCLK - Input pin valid when XENDEC is not zero (0).
Pwrdwn bits in ECSR
Enable Function bit in ECOR
PWRDN - Legacy power down bit in Control Register.
All internal logic
The Ethernet controller function and
Ethernet PCMCIA Configuration Registers
except for the bit itself. Setting this bit also
lowers the nIREQ/READY line. When
cleared, the nIREQ/READY line is raised.
The Ethernet controller itself except for
the IA, CONF and BASE registers. It does
not reset any PCMCIA Configuration
Register.
RESETS THE FOLLOWING
nIREQ when function is Ready.
Acts as ready line at power up.
I.e. remains low until the chip
(therefore, card) is Ready
OR function of all interrupt bits specified in the Interrupt Status Register
ANDed with their respective Enable bits
FUNCTIONS
Table 5.5 - Interrupt Merging
DATASHEET
PCMCIA MODE
Page 32
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Intr bit in ECSR
LOCAL BUS
VS. PCMCIA
SAMPLES
INTR0-3
Not Applicable in LOCAL BUS
mode
MODE
Yes
No
No
LOCAL BUS MODE
TRIGGERS
EEPROM
READ
Yes
Yes
No
SMSC LAN91C96 5v&3v
Datasheet
The