LAN9210-ABZJ Standard Microsystems (SMSC), LAN9210-ABZJ Datasheet - Page 13

• Manufacturer Part Number: LAN9210-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9210-ABZJ

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9210
1.11
The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as
an interface for the LAN9210 Control and Status Registers (CSR’s).
The host bus interface is the primary bus for connection to the embedded host system. This interface
models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface.
Programmed I/O transactions are supported.
The LAN9210 host bus interface supports 16-bit bus transfers. Internally, all data paths are 32-bits
wide. The LAN9210 can be interfaced to either Big-Endian or Little-Endian processors and includes
mixed endian support for FIFO accesses.
Host Bus Interface (SRAM Interface)
DATASHEET
13
Revision 2.7 (03-15-10)