CY7C924ADX-AC Cypress Semiconductor Corp, CY7C924ADX-AC Datasheet - Page 10

• Manufacturer Part Number: CY7C924ADX-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AC

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
Pin Descriptions
CY7C924ADX HOTLink Transceiver
75
74
49
28
27
24, 25
Number
Pin
SPDSEL
RANGESEL
EXTFIFO
FIFOBYP*
ENCBYP*
RXMODE[1:0]
Name
(continued)
Static control input
TTL levels Normally
wired HIGH or LOW
Static control input
TTL levels Normally
wired HIGH or LOW
Static control input
TTL levels Normally
wired HIGH or LOW
Static control input
TTL levels Normally
wired HIGH or LOW
Static control input
TTL levels Normally
wired HIGH or LOW
Static control input
TTL levels Normally
wired HIGH or LOW
I/O Characteristics
Speed Select. Selects one of two operating data rate ranges for the device.
When the operating symbol rate is between 100 and 200 MBaud, SPDSEL
must be HIGH. When the operating symbol rate is between 50 and 100
MBaud, SPDSEL must be LOW (see
Range Select. Selects the proper prescaler for the REFCLK input. See
Table 5
FIFOBYP*, ENCBYP* and BYTE8/10*.
When the Transmit FIFO is bypassed (FIFOBYP* is LOW) and REFCLK is a
nonunity multiple of the character rate (RANGESEL HIGH or SPDSEL LOW),
TXFULL* toggles at half the REFCLK rate to provide a character rate
indication, and to show when data can be accepted.
External FIFO Select. EXTFIFO indicates whether the device is used with
external FIFOs. It modifies the active level of the RXEN* and TXEN* inputs
and the timing of the Transmitter data bus according to the interface selected.
When in UTOPIA mode and not configured for external FIFOs (EXTFIFO is
LOW), TXEN*, RXEN* and all FIFO flags are active LOW. In this mode the
active data transition for the transmit data bus is within the same clock as the
transmit interface is selected by TXEN*.
When configured for Cascade mode where the CY7C924ADX device is
cascaded with external FIFOs (EXTFIFO is HIGH), TXEN, RXEN, the Full and
Empty FIFO flags are active HIGH (the Half-full flag is always active LOW).
TXEN is driven by the empty flag of an attached CY7C42X5 FIFO, and RXEN
is driven by the Almost Full flag of an attached CY7C42X5 FIFO. In this mode
the active data transition for the transmit data bus is in the clock cycle following
the clock edge where transmit interface is selected by TXEN*.
FIFO Bypass Select. When LOW, the Transmit and Receive FIFOs are
bypassed. In this mode TXCLK is not used. Instead all transmit data must be
synchronous to REFCLK. Transmit FIFO status flags are synchronized to
REFCLK. RXCLK becomes an output at the Receive PLL recovered character
clock rate. All received data and FIFO status flags are synchronized to
RXCLK.
When HIGH, the Transmit and Receive FIFOs are enabled. In this mode all
Transmit FIFO writes are synchronized to TXCLK, and all Receive FIFO reads
are synchronous to the RXCLK input.
Encoder Bypass Select. When LOW, both the encoder and decoder are
bypassed. Data transmits in NRZ format, without encoding, LSB first.
Received data are presented to the interface as parallel characters without
decoding.
When HIGH, data passes through both the 8B/10B encoder in the Transmit
path and the decoder in the Receive path.
Receive Discard Policy Select. These inputs select among the four data
handling and fill-character discard modes in the receiver. See
23.
for the various relationships among REFCLK, SPDSEL, RANGESEL,
Signal Description
Table 5 on page
CY7C924ADX
19).
Table 7 on page
Page 10 of 58
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