KSZ8995XA B3 Micrel Inc, KSZ8995XA B3 Datasheet - Page 4

• Manufacturer Part Number: KSZ8995XA B3
• Manufacturer: Micrel Inc

Specifications of KSZ8995XA B3

• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

September 2008
Contents
System Level Applications........................................................................................................................................... 6
Pin Configuration .......................................................................................................................................................... 8
Pin Description (by Number)........................................................................................................................................ 9
Pin Description (by Name) ......................................................................................................................................... 14
Introduction ................................................................................................................................................................. 19
Functional Overview: Physical Layer Transceiver .................................................................................................. 19
Functional Overview: Switch Core ............................................................................................................................ 21
SNI Interface Operation .............................................................................................................................................. 26
Advanced Functionality.............................................................................................................................................. 26
Register Map................................................................................................................................................................ 30
100BASE-TX Transmit.............................................................................................................................................. 19
100BASE-TX Receive............................................................................................................................................... 19
PLL Clock Synthesizer.............................................................................................................................................. 19
Scrambler/De-Scrambler (100BASE-TX only).......................................................................................................... 19
100BASE-FX Operation............................................................................................................................................ 20
100BASE-FX Signal Detection ................................................................................................................................. 20
100BASE-FX Far End Fault...................................................................................................................................... 20
10BASE-T Transmit .................................................................................................................................................. 20
10BASE-T Receive ................................................................................................................................................... 20
Power Management.................................................................................................................................................. 20
MDI/MDI-X Auto Crossover ...................................................................................................................................... 20
Auto-Negotiation ....................................................................................................................................................... 20
Address Look-Up ...................................................................................................................................................... 21
Learning .................................................................................................................................................................... 21
Migration ................................................................................................................................................................... 21
Aging ......................................................................................................................................................................... 21
Switching Engine ...................................................................................................................................................... 22
Media Access Controller (MAC) Operation............................................................................................................... 22
Inter-Packet Gap (IPG) ............................................................................................................................................. 22
Backoff Algorithm ...................................................................................................................................................... 22
Late Collision ............................................................................................................................................................ 22
Illegal Frames ........................................................................................................................................................... 22
Flow Control .............................................................................................................................................................. 22
Half-Duplex Back Pressure ....................................................................................................................................... 22
Broadcast Storm Protection ...................................................................................................................................... 23
MII Interface Operation ............................................................................................................................................. 24
QoS Support ............................................................................................................................................................. 26
Rate Limit Support .................................................................................................................................................... 28
Configuration Interface.............................................................................................................................................. 29
I
MII Management Interface (MIIM) ............................................................................................................................ 29
Global Registers ....................................................................................................................................................... 30
Register 0 (0x00): Chip ID0 ...................................................................................................................................... 30
Register 1 (0x01): Chip ID1/Start Switch .................................................................................................................. 30
Register 2 (0x02): Global Control 0 .......................................................................................................................... 30
Register 3 (0x03): Global Control 1 .......................................................................................................................... 31
Register 4 (0x04): Global Control 2 .......................................................................................................................... 32
Register 5 (0x05): Global Control 3 .......................................................................................................................... 33
Register 6 (0x06): Global Control 4 .......................................................................................................................... 33
Register 7 (0x07): Global Control 5 .......................................................................................................................... 34
Register 8 (0x08): Global Control 6 .......................................................................................................................... 34
Register 9 (0x09): Global Control 7 .......................................................................................................................... 34
Register 10 (0x0A): Global Control 8 ........................................................................................................................ 34
2
C Master Serial Bus Configuration ......................................................................................................................... 29
4
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